Semiconductor structure and method for manufacturing the same
View Patent ↗A method for manufacturing a semiconductor structure includes defining active areas extending in an X-direction, arranged in a Y-direction, and on a substrate. Each of the active areas has nanostructures. The method further includes forming dummy gate structures across the active areas in the Y-direction, forming merged source/drain features in the active areas and on opposite sides of the dummy gate structures in the X-direction, forming dielectric structures in the active areas to cut each of the merged source/drain features into a first source/drain feature and a second source/drain feature, and to cut each of the dummy gate structures into segments, and replacing the segments of the dummy gate structures with gate structures wrapping around the nanostructures in the active areas. The dielectric structures are in contact with sidewalls of the first source/drain features, the second source/drain features, and the gate structures.
1 . A method for manufacturing a semiconductor structure, comprising:
defining active areas extending in a first direction, arranged in a second direction, and on a substrate, wherein each of the active areas has nanostructures;
forming dummy gate structures across the active areas in the second direction;
forming merged source/drain features in the active areas and on opposite sides of the dummy gate structures in the first direction;
forming dielectric structures in the active areas to cut each of the merged source/drain features into a first source/drain feature and a second source/drain feature, and to cut each of the dummy gate structures into segments; and
replacing the segments of the dummy gate structures with gate structures wrapping around the nanostructures in the active areas, wherein the dielectric structures are in contact with sidewalls of the first source/drain features, the second source/drain features, and the gate structures.
2 . The method of claim 1 , wherein the nanostructures are in contact with sidewalls of the dielectric structures.
3 . The method of claim 1 , wherein the nanostructures are separated from the dielectric structures in the second direction.
4 . The method of claim 1 , wherein bottom surfaces of the dielectric structures are in contact with the substrate.
5 . The method of claim 1 , further comprising:
forming a source/drain contact over one of the dielectric structures and one of the first source/drain features in contact with the one of the dielectric structures.
6 . The method of claim 5 , wherein the source/drain contact is over one of the second source/drain features in contact with the one of the dielectric structures.
7 . The method of claim 5 , wherein the source/drain contact is further over one of the second source/drain features in contact with another one of the dielectric structures.
8 . The method of claim 1 , wherein the dielectric structures are first dielectric structures, and the method further comprises:
forming an isolation structure between the active areas; and
forming a second dielectric structure between adjacent two of the active areas and in contact with the isolation structure.
9 . The method of claim 8 , wherein the second dielectric structure is in contact with the substrate.
10 . The method of claim 1 , wherein the dielectric structures comprise Si3N4, SiO2, SiOC, SION, SiOCN, or combinations thereof.
11 . A method for manufacturing a semiconductor structure, comprising:
forming nanostructures in an active area extending in a first direction and on a substrate;
forming a dummy gate structure extending in a second direction and across the active area in a top view;
forming a merged source/drain feature attached to the nanostructures;
forming a dielectric structure extending in the first direction and in the active area to cut the merged source/drain feature into a first source/drain feature and a second source/drain feature on opposite sides of the dielectric structure in the second direction and to cut the dummy gate structure into a first segment and a second segment by the dielectric structure;
replacing the first segment and the second segment to form a first gate structure and a second gate structure extending in the second direction, wherein each of the first gate structure and the second gate structure wraps around the nanostructures; and
forming a metal conductor over the dielectric structure,
wherein the dielectric structure is in contact with sidewalls of the first source/drain feature, the second source/drain feature, the first gate structure, and the second gate structure.
12 . The method of claim 11 , further comprising:
forming a source/drain contact in contact with and over the dielectric structure and the first source/drain feature, wherein the metal conductor is electrically connected to the source/drain contact.
13 . The method of claim 12 , wherein the source/drain contact partially covers the dielectric structure.
14 . The method of claim 11 , wherein a distance from a top surface of the dielectric structure to top surfaces of the first source/drain feature and the second source/drain feature in a third direction is in a range from about 5 nm to about 50 nm.
15 . The method of claim 11 , wherein a width of the dielectric structure in the second direction is in a range from about 10 nm to about 60 nm.
16 . The method of claim 11 , wherein a distance from a bottom surface of the dielectric structure to a topmost surface of the substrate in a third direction is in a range from about 10 nm to about 150 nm.
17 . The method of claim 11 , wherein a bottom surface of the dielectric structure is in contact with the substrate.
18 . A method, comprising:
forming a first dummy gate structure extending in a first direction across a cell boundary and a second dummy gate structure extending in the first direction across the cell boundary and offset from the first dummy gate structure;
replacing a first portion of the second dummy gate structure on a first side of the cell boundary with a dielectric gate structure;
forming a merged source/drain feature extending in the first direction across the cell boundary and positioned between the first dummy gate structure, the second dummy gate structure, and the dielectric gate structure; and
forming a trench that extends in the first direction along the cell boundary to define:
a first source/drain feature and a second source/drain feature each formed from the merged source/drain feature,
a first segment and a second segment each formed from the first dummy gate structure, and
a third segment formed from a second portion of the second dummy gate structure on a second side of the cell boundary.
19 . The method of claim 18 , comprising:
forming a dielectric structure in the trench.
20 . The method of claim 18 , comprising:
forming vertically stacked semiconductor layers extending across the cell boundary;
wherein forming the trench comprises:
defining first nanostructures and second nanostructures from the vertically stacked semiconductor layers.