Silicon-on-insulator substrate processing for transistor enhancement
Silicon-on-insulator (SOI) substrate processing for transistor enhancement is disclosed. In certain embodiments, a silicon substrate for an SOI process is separated into sub-regions or islands by dielectric. Thus, the substrate is changed from having one region and one shared contact into multiple substrate sub-regions with independent contacts. Since the substrate serves as a back gate to SOI transistors formed in an active silicon layer, breaking the substrate into independent or separate islands leads to a drop in the impact of each island on the drain-to-source voltage and/or gate-to-source voltage of the SOI transistors. Accordingly, reduced harmonics and improved linearity are achieved.
1 . A silicon-on-insulator wafer comprising:
a silicon substrate broken into two or more substrate regions by a dielectric, the two or more substrate regions including a plurality of islands that are laterally isolated from one another on all sides by the dielectric;
a buried oxide layer formed over the silicon substrate; and
an active silicon layer formed over the buried oxide layer and including a plurality of silicon-on-insulator transistors, the plurality of islands forming a plurality of isolation resistors that provide isolation between two or more gates of the plurality of silicon-on-insulator transistors.
2 . The silicon-on-insulator wafer of claim 1 wherein the dielectric is formed in a focused ion beam etched region.
3 . The silicon-on-insulator wafer of claim 1 wherein the dielectric is formed in a deep trench region.
4 . The silicon-on-insulator wafer of claim 1 wherein at least one silicon-on-insulator transistor of the plurality of silicon-on-insulator transistors is arranged as a switch.
5 . The silicon-on-insulator wafer of claim 1 wherein only a portion of the silicon-on-insulator wafer includes the broken silicon substrate.
6 . The silicon-on-insulator wafer of claim 1 wherein the broken silicon substrate extends across an entirety of the silicon-on-insulator wafer.
7 . The silicon-on-insulator wafer of claim 1 wherein the silicon-on-insulator wafer includes two or more breaking patterns for breaking the silicon substrate.
8 . A packaged radio frequency module comprising:
a package substrate; and
a silicon-on-insulator die attached to the package substrate, the silicon-on-insulator die including a silicon substrate broken into two or more substrate regions by a dielectric, the two or more substrate regions including a plurality of islands that are laterally isolated from one another on all sides by the dielectric, the silicon-on-insulator die further including a buried oxide layer formed over the silicon substrate, and an active silicon layer formed over the buried oxide layer and including a plurality of silicon-on-insulator transistors, the plurality of islands forming a plurality of isolation resistors that provide isolation between two or more gates of the plurality of silicon-on-insulator transistors.
9 . The packaged radio frequency module of claim 8 wherein the dielectric is formed in a focused ion beam etched region.
10 . The packaged radio frequency module of claim 8 wherein the dielectric is formed in a deep trench region.
11 . The packaged radio frequency module of claim 8 wherein at least one silicon-on-insulator transistor of the plurality of silicon-on-insulator transistors is arranged as a switch.
12 . The packaged radio frequency module of claim 8 wherein the silicon-on-insulator die includes two or more breaking patterns for breaking the silicon substrate.
13 . The packaged radio frequency module of claim 8 wherein only a portion of the silicon-on-insulator die includes the broken silicon substrate.
14 . A method of processing a silicon-on-insulator wafer, the method comprising:
forming a buried oxide layer formed over a silicon substrate;
forming an active silicon layer over the buried oxide layer, the active silicon layer including a plurality of silicon-on-insulator transistors; and
breaking the silicon substrate into two or more substrate regions separated by a dielectric, the two or more substrate regions including a plurality of islands that are laterally isolated from one another on all sides by the dielectric, the plurality of islands forming a plurality of isolation resistors that provide isolation between two or more gates of the plurality of silicon-on-insulator transistors.
15 . The method of claim 14 wherein the silicon-on-insulator wafer includes two or more breaking patterns for breaking the silicon substrate.
16 . The method of claim 14 further comprising forming at least one silicon-on-insulator transistor of the plurality of silicon-on-insulator transistors as a switch.
17 . The method of claim 14 wherein breaking the silicon substrate includes etching a bottom surface of the silicon substrate using a focused ion beam, and filling the etched silicon substrate with the dielectric.
18 . The method of claim 14 wherein breaking the silicon substrate includes forming a plurality of deep trenches in a top surface of the silicon substrate, and filling the plurality of deep trenches with the dielectric.
19 . The method of claim 14 wherein the broken silicon substrate extends across an entirety of the silicon-on-insulator wafer.
20 . The method of claim 14 wherein only a portion of the silicon-on-insulator wafer includes the broken silicon substrate.