Display panel and display device
A display panel comprises a substrate including a display area where a plurality of subpixels are disposed, a gate driving circuit disposed in a non-display area outside the display area to supply a plurality of scan signals to the plurality of subpixels, and a plurality of pads disposed in the non-display area and coupled with a plurality of signal lines electrically connected to the gate driving circuit and an electrostatic discharge unit, wherein the plurality of pads include a clock pad connected with a clock signal line, a first line pad connected with a plurality of first power lines and where at least one low-potential signal line is disposed between adjacent gate high-potential voltage lines among the plurality of first power lines, and a second line pad connected with a plurality of second power lines.
1 . A display panel, comprising:
a substrate including a display area where a plurality of subpixels are disposed;
a gate driving circuit in a non-display area that is outside the display area, the gate driving circuit configured to supply a plurality of scan signals to the plurality of subpixels; and
a plurality of pads in the non-display area and coupled with a plurality of signal lines that are electrically connected to the gate driving circuit, the plurality of pads including:
a clock pad connected with a clock signal line;
a first line pad connected with a plurality of first power lines and at least one low-potential signal line is between adjacent gate high-potential voltage lines among the plurality of first power lines; and
a second line pad connected with a plurality of second power lines,
wherein the clock signal line includes a carry clock signal line, a scan clock signal line, and a sensing clock signal line, and the scan clock signal line is positioned between the carry clock signal line and the sensing clock signal line, and
wherein a width of the scan clock signal line is larger than a width of the carry clock signal line, and a width of the sensing clock signal line is larger than the width of the carry clock signal line.
2 . The display panel of claim 1 , wherein the gate driving circuit includes a plurality of gate driving panel circuits generating at least one scan signal.
3 . The display panel of claim 2 , wherein the plurality of gate driving panel circuits include a first gate driving panel circuit and a second gate driving panel circuit,
wherein when a first node of the first gate driving panel circuit has a high-level voltage, the first gate driving panel circuit outputs a first scan signal having the high-level voltage, and when a first node of the second gate driving panel circuit has the high-level voltage, the second gate driving panel circuit outputs a second scan signal having the high-level voltage.
4 . The display panel of claim 3 , wherein a high-level voltage section of the first scan signal and a high-level voltage section of the second scan signal temporally overlap each other.
5 . The display panel of claim 4 , wherein a temporal length of the high-level voltage section of each of the first scan signal and the second scan signal is a 2-horizontal time length, and
wherein the high-level voltage section of the first scan signal overlaps the high-level voltage section of the second scan signal for a 1 horizontal time.
6 . The display panel of claim 2 , wherein the plurality of gate driving panel circuits include:
an output buffer block configured to output the at least one scan signal according to a voltage state of a first node and a second node;
a logic block configured to control voltages of the first node and the second node; and
a real-time sensing control block configured to control the logic block to perform real-time sensing driving.
7 . The display panel of claim 6 , wherein the first node is a Q node that controls a pull-up transistor of the output buffer block.
8 . The display panel of claim 7 , wherein the pull-up transistor of the output buffer block includes a carry pull-up transistor, a scan pull-up transistor, and a sensing pull-up transistor, and
wherein a gate node of the carry pull-up transistor, a gate node of the scan pull-up transistor, and a gate node of the sensing pull-up transistor are connected to each other and electrically connected to the Q node in common.
9 . The display panel of claim 7 , wherein the second node is a QB node that controls a pull-down transistor of the output buffer block.
10 . The display panel of claim 9 , wherein the pull-down transistor of the output buffer block includes a carry pull-down transistor, a scan pull-down transistor, and a sensing pull-down transistor, and
wherein a gate node of the carry pull-down transistor, a gate node of the scan pull-down transistor, and a gate node of the sensing pull-down transistor are connected to each other and electrically connected to the QB node in common.
11 . The display panel of claim 6 , wherein the output buffer block includes:
a carry output buffer configured to output a carry signal; and
a scan output buffer configured to output the at least one scan signal.
12 . The display panel of claim 11 , wherein the output buffer block further includes:
a sensing output buffer configured to output a sensing signal having a turn-on level voltage or a turn-off level voltage.
13 . The display panel of claim 1 , wherein the clock pad includes:
a carry clock pad connected with a carry clock signal line that transfers a carry clock signal to the gate driving circuit; and
a scan clock pad connected with a scan clock signal line that transfers a scan clock signal to the gate driving circuit.
14 . The display panel of claim 13 , wherein the clock pad further includes:
a sensing clock pad connected to a sensing clock signal line that transfers a sensing clock signal to the gate driving circuit.
15 . The display panel of claim 6 , wherein the first line pad includes:
a gate high-potential voltage pad connected with a gate high-potential voltage line that transfers a gate high-potential voltage to the gate driving circuit;
a start signal pad connected with a start signal line that transfers a start signal to the gate driving circuit;
a reset signal pad connected with a reset signal line that transfers a reset signal to the gate driving circuit; and
a line selection signal pad connected with a line selection signal line that transfers a line selection signal to the gate driving circuit.
16 . A display panel comprising:
a substrate including a display area where a plurality of subpixels are disposed;
a gate driving circuit in a non-display area that is outside the display area, the gate driving circuit includes a plurality of gate driving panel circuits configured to supply a plurality of scan signals to the plurality of subpixels; and
a plurality of pads in the non-display area and coupled with a plurality of signal lines that are electrically connected to the gate driving circuit,
wherein the plurality of pads include:
a clock pad connected with a clock signal line;
a first line pad connected with a plurality of first power lines and at least one low-potential signal line is between adjacent gate high-potential voltage lines among the plurality of first power lines; and
a second line pad connected with a plurality of second power lines,
wherein the first line pad includes:
a gate high-potential voltage pad connected with a gate high-potential voltage line that transfers a gate high-potential voltage to the gate driving circuit;
a start signal pad connected with a start signal line that transfers a start signal to the gate driving circuit;
a reset signal pad connected with a reset signal line that transfers a reset signal to the gate driving circuit; and
a line selection signal pad connected with a line selection signal line that transfers a line selection signal to the gate driving circuit,
wherein the gate high-potential voltage line includes:
a first gate high-potential voltage line that transfers a first gate high-potential voltage that charges a first node;
a second gate high-potential voltage line that transfers a second gate high-potential voltage that stabilizes a transistor controlling the first node; and
a third gate high-potential voltage line that transfers a third gate high-potential voltage that charges a second node.
17 . The display panel of claim 16 , wherein the second gate high-potential voltage line includes:
a 2-1th gate high-potential voltage line that transfers a 2-1th gate high-potential voltage applied at a high level at an odd-numbered horizontal time; and
a 2-2th gate high-potential voltage line that transfers a 2-2th gate high-potential voltage applied at a high level at an even-numbered horizontal time.
18 . The display panel of claim 17 , wherein the plurality of gate driving panel circuits include:
an output buffer block configured to output at least one scan signal according to a voltage state of the first node and the second node;
a logic block configured to control voltages of the first node and the second node; and
a real-time sensing control block configured to control the logic block to perform real-time sensing driving,
wherein the logic block include:
a first group of transistors outputting a scan signal by the 2-1th gate high-potential voltage; and
a second group of transistors outputting a scan signal by the 2-2th gate high-potential voltage.
19 . The display panel of claim 18 , wherein the first group of transistors and the second group of transistors are alternately driven.
20 . The display panel of claim 19 , wherein the first group of transistors are driven at the odd-numbered horizontal time, and the second group of transistors are driven at the even-numbered horizontal time.
21 . The display panel of claim 17 , wherein the start signal line is between the 2-1th gate high-potential voltage line and the 2-2th gate high-potential voltage line.
22 . The display panel of claim 17 , wherein the reset signal line is between the 2-1th gate high-potential voltage line and the 2-2th gate high-potential voltage line.
23 . The display panel of claim 1 , further comprising:
an electrostatic discharge circuit in the non-display area; and
an additional pad connected with an electrostatic discharge high-potential voltage line that transfers an electrostatic discharge high-potential voltage to the electrostatic discharge circuit and an electrostatic discharge low-potential voltage line that transfers an electrostatic discharge low-potential voltage to the electrostatic discharge circuit.
24 . The display panel of claim 23 , wherein the additional pad includes:
an electrostatic discharge high-potential voltage pad connected with the electrostatic discharge high-potential voltage line;
an electrostatic discharge low-potential voltage pad connected with the electrostatic discharge low-potential voltage line; and
at least one dummy pad positioned between the electrostatic discharge high-potential voltage pad and the electrostatic discharge low-potential voltage pad.
25 . The display panel of claim 1 , wherein the second line pad includes:
a first gate low-potential voltage pad connected with a first gate low-potential voltage line that transfers a first gate low-potential voltage to the gate driving circuit;
a second gate low-potential voltage pad connected with a second gate low-potential voltage line that transfers a second gate low-potential voltage to the gate driving circuit; and
a third gate low-potential voltage pad connected with a third gate low-potential voltage line that transfers a third gate low-potential voltage to the gate driving circuit.
26 . The display panel of claim 1 , wherein the clock signal line and a first power line from the plurality of first power lines are on one side of the gate driving circuit, and a second power line from the plurality of second power lines is on another side of the gate driving circuit.
27 . The display panel of claim 1 , wherein the plurality of pads further include a second additional pad between the second line pad and the display area.
28 . The display panel of claim 1 , wherein the plurality of pads further include a ground pad that is further outside the clock pad.
29 . A display device, comprising:
a display panel including a plurality of subpixels in a display area and a plurality of pads coupled with a plurality of signal lines in a non-display area that is outside the display area;
a gate driving circuit configured to supply a plurality of scan signals to the display panel through a plurality of gate lines;
a data driving circuit configured to supply a plurality of data voltages to the display panel through a plurality of data lines; and
a controller configured to control the gate driving circuit and the data driving circuit,
wherein the plurality of pads include:
a clock pad connected with a clock signal line;
a first line pad connected with a plurality of first power lines where at least one low-potential signal line is between adjacent gate high-potential voltage lines among the plurality of first power lines; and
a second line pad connected with a plurality of second power lines,
wherein the first line pad includes:
a gate high-potential voltage pad connected with a gate high-potential voltage line that transfers a gate high-potential voltage to the gate driving circuit;
a start signal pad connected with a start signal line that transfers a start signal to the gate driving circuit;
a reset signal pad connected with a reset signal line that transfers a reset signal to the gate driving circuit; and
a line selection signal pad connected with a line selection signal line that transfers a line selection signal to the gate driving circuit,
wherein the gate high-potential voltage line includes:
a first gate high-potential voltage line that transfers a first gate high-potential voltage that charges a first node;
a second gate high-potential voltage line that transfers a second gate high-potential voltage that stabilizes a transistor controlling the first node; and
a third gate high-potential voltage line that transfers a third gate high-potential voltage that charges a second node.