Array substrate and display panel

1 . An array substrate, comprising a base substrate and a pixel circuit disposed on the base substrate, wherein the pixel circuit comprises a driving circuit and a light sensing circuit, and the light sensing circuit comprises a first transistor, a second transistor, and a first capacitor,

wherein a gate of the first transistor is connected to a first control signal line, a first electrode of the first transistor is connected to a first power line, and a second electrode of the first transistor is connected to a first electrode of the second transistor;

wherein the first capacitor comprises a first electrode plate and a second electrode plate, the first electrode plate is connected to the second electrode of the first transistor and the first electrode of the second transistor, and the second electrode plate is connected to a common voltage signal line;

wherein the first electrode plate and the second electrode plate are both transparent electrode plates, and the driving circuit and the light sensing circuit share the common voltage signal line; and

wherein the common voltage signal line is entirely disposed in a same layer as the gate of the first transistor;

wherein an orthographic projection of the first capacitor on the base substrate entirely covers an orthographic projection of the first transistor on the base substrate.

2 . The array substrate according to claim 1 , wherein the light sensing circuit further comprises a readout circuit, a second electrode of the second transistor is connected to the readout circuit, and a gate of the second transistor is connected to a second control signal line.

3 . The array substrate according to claim 1 , wherein the array substrate further comprises a light sensing unit, the light sensing circuit is disposed in the light sensing unit, the first transistor and the second transistor are disposed in a same layer, and the first capacitor is disposed at a side of the first transistor and the second transistor, wherein the side is farther away from the base substrate than a further side of the first transistor and the second transistor.

4 . The array substrate according to claim 3 , wherein the array substrate further comprises:

a first inorganic layer disposed on the side of the first transistor and the second transistor; and

a second inorganic layer disposed on a side of the first inorganic layer away from the first transistor and located between the first electrode plate and the second electrode plate.

5 . The array substrate according to claim 4 , wherein the array substrate further comprises a display unit, the driving circuit is disposed in the display unit, and the display unit comprises:

a third transistor disposed in the same layer as the first transistor;

a pixel electrode disposed in a same layer as the first electrode plate or the second electrode plate; and

a common electrode also serving as the second electrode plate.

6 . The array substrate according to claim 5 , wherein the first electrode plate is disposed on the first inorganic layer, and the second electrode plate is disposed on the second inorganic layer.

7 . The array substrate according to claim 5 , wherein the second electrode plate is disposed on the first inorganic layer, and the first electrode plate is disposed on the second inorganic layer.

8 . The array substrate according to claim 5 , wherein the first electrode plate, the common electrode, and the pixel electrode are made of a same material.

9 . The array substrate according to claim 4 , wherein the array substrate further comprises a display unit, the driving circuit is disposed in the display unit, and the display unit comprises:

a third transistor disposed in the same layer as the first transistor;

a pixel electrode disposed above the third transistor and electrically connected to the third transistor; and

a common electrode also serving as the second electrode plate,

wherein the pixel electrode is disposed in a layer different from the first electrode plate and the second electrode plate.

10 . A display panel, comprising an array substrate, wherein the array substrate comprises a base substrate and a pixel circuit disposed on the base substrate, the pixel circuit comprises a driving circuit and a light sensing circuit, and the light sensing circuit comprises a first transistor, a second transistor, and a first capacitor,

wherein a gate of the first transistor is connected to a first control signal line, a first electrode of the first transistor is connected to a first power line, and a second electrode of the first transistor is connected to a first electrode of the second transistor;

wherein the first capacitor comprises a first electrode plate and a second electrode plate, the first electrode plate is connected to the second electrode of the first transistor and the first electrode of the second transistor, and the second electrode plate is connected to a common voltage signal line;

wherein the first electrode plate and the second electrode plate are both transparent electrode plates, and the driving circuit and the light sensing circuit share the common voltage signal line; and

wherein the common voltage signal line is entirely disposed in a same layer as the gate of the first transistor;

wherein an orthographic projection of the first capacitor on the base substrate entirely covers an orthographic projection of the first transistor on the base substrate.

11 . The display panel according to claim 10 , wherein the light sensing circuit further comprises a readout circuit, a second electrode of the second transistor is connected to the readout circuit, and a gate of the second transistor is connected to a second control signal line.

12 . The display panel according to claim 10 , wherein the array substrate further comprises a light sensing unit, the light sensing circuit is disposed in the light sensing unit, the first transistor and the second transistor are disposed in a same layer, and the first capacitor is disposed at a side of the first transistor and the second transistor, wherein the side is farther away from the base substrate than a further side of the first transistor and the second transistor.

13 . The display panel according to claim 12 , wherein the array substrate further comprises:

a first inorganic layer disposed on the side of the first transistor and the second transistor; and

a second inorganic layer disposed on a side of the first inorganic layer away from the first transistor and located between the first electrode plate and the second electrode plate.

14 . The display panel according to claim 13 , wherein the array substrate further comprises a display unit, the driving circuit is disposed in the display unit, and the display unit comprises:

a third transistor disposed in the same layer as the first transistor;

a pixel electrode disposed in a same layer as the first electrode plate or the second electrode plate; and

a common electrode also serving as the second electrode plate,

wherein the display panel is time-divided into a display stage and a light sensing stage within one frame time, the display unit is used to work in the display stage, and the light sensing unit is used to work in the light sensing stage.

15 . The display panel according to claim 14 , wherein the first electrode plate is disposed on the first inorganic layer, and the second electrode plate is disposed on the second inorganic layer.

16 . The display panel according to claim 14 , wherein the second electrode plate is disposed on the first inorganic layer, and the first electrode plate is disposed on the second inorganic layer.

17 . The display panel according to claim 14 , wherein the first electrode plate, the common electrode, and the pixel electrode are made of a same material.

18 . The display panel according to claim 13 , wherein the array substrate further comprises a display unit, the driving circuit is disposed in the display unit, and the display unit comprises:

a third transistor disposed in the same layer as the first transistor;

a pixel electrode disposed above the third transistor and electrically connected to the third transistor; and

a common electrode also serving as the second electrode plate,

wherein the pixel electrode is disposed in a layer different from the first electrode plate and the second electrode plate.