CMOS image sensors and manufacturing methods thereof
Various embodiments of the present disclosure are directed towards an integrated circuit on a semiconductor substrate. First and second gate electrode structures are disposed over the substrate and are spaced laterally from one another. A common source/drain region is disposed in the semiconductor substrate between the first and second gate electrode structures. An insulator layer overlies the first and second gate electrode structures. A source/drain contact extends through the insulator layer between the first and second gate electrode structures to contact the common source/drain region. First and second sidewall spacer structures are disposed along outer sidewalls of the first and second gate electrode structures, respectively, and have first and second outer sidewalls, respectively, adjacent to the source/drain contact. The first outer sidewall includes at least two indentations facing a first side of the source/drain contact, and the second outer sidewall includes at least two indentations facing a second side of the source/drain contact.
1 . An integrated circuit, comprising:
a semiconductor substrate;
first and second gate electrode structures disposed over the semiconductor substrate and spaced apart laterally from one another;
a common source/drain region disposed in the semiconductor substrate between the first and second gate electrode structures;
an insulator layer overlying the first and second gate electrode structures;
a source/drain contact extending through the insulator layer between the first and second gate electrode structures to contact the common source/drain region; and
first and second sidewall spacer structures disposed along outer sidewalls of the first and second gate electrode structures, respectively, and having a material defining first and second outer sidewalls, respectively, adjacent to the source/drain contact; and
wherein the material defining the first outer sidewall includes at least three indentations along the first outer sidewall facing a first side of the source/drain contact and wherein the material defining the second outer sidewall includes at least three indentations along the second outer sidewall facing a second side of the source/drain contact.
2 . The integrated circuit of claim 1 , wherein the first sidewall spacer structure comprises:
a first conformal layer along the first outer sidewall of the first gate electrode structure and extending laterally over an upper surface of the first gate electrode structure; and
a second conformal layer that corresponds to the material, the second conformal layer extending over an upper surface of the first conformal layer and extending laterally over the upper surface of the first conformal layer over the first gate electrode structure, the material of the second conformal layer differing from a material of the first conformal layer.
3 . The integrated circuit of claim 2 , wherein a first indentation of the at least three indentations on the first outer sidewall corresponds to a first inner corner of the second conformal layer where a lateral surface of the second conformal layer meets a sidewall of the second conformal layer.
4 . The integrated circuit of claim 3 , wherein a second indentation of the at least three indentations on the first outer sidewall corresponds to a second inner corner of the second conformal layer, the second inner corner being disposed above the first inner corner.
5 . The integrated circuit of claim 2 , wherein the first conformal layer comprises a base portion and a collar portion extending upward from the base portion, the base portion and the collar portion each laterally surrounding the first gate electrode structure, wherein the base portion is wider than the collar portion such that an upper surface of the base portion corresponds to a ledge.
6 . The integrated circuit of claim 5 , wherein the collar portion has a thickness between its sidewalls and wherein nearest outer sidewalls of the first and second gate electrode structures are separated by a lateral spacing, wherein a ratio of the thickness to the lateral spacing ranges from 1:20 to 3:20.
7 . The integrated circuit of claim 5 , further comprising:
a nitride sidewall spacer disposed on the ledge and disposed between some portions of the first conformal layer and the second conformal layer.
8 . The integrated circuit of claim 1 , wherein the at least three indentations along the first outer sidewall have respective heights as measured from an upper surface of the semiconductor substrate that correspond to heights within the first and second gate electrode structures.
9 . The integrated circuit of claim 8 , wherein the first sidewall spacer structure comprises: a first conformal layer along the first outer sidewall of the first gate electrode structure; and a second conformal layer extending over an upper surface of the first conformal layer and extending laterally over an upper surface of the first gate electrode structure; and further comprising:
a contact etch stop layer disposed over the second conformal layer.
10 . The integrated circuit of claim 1 , wherein the first outer sidewall includes at least four indentations along the first outer sidewall and facing the first side of the source/drain contact, and wherein the second outer sidewall includes at least four indentations along the second outer sidewall and facing the second side of the source/drain contact.
11 . The integrated circuit of claim 1 , further comprising:
a photodetector disposed in the semiconductor substrate.
12 . An integrated circuit, comprising:
a semiconductor substrate;
first and second gate electrode structures disposed over first and second channel regions in the semiconductor substrate, the first and second channel regions having a first conductivity type;
a doped region disposed in the semiconductor substrate between the first and second channel regions, the doped region having a second conductivity type opposite the first conductivity type;
a dielectric layer overlying the first and second gate electrode structures;
a contact extending through the dielectric layer between nearest neighboring sidewalls of the first and second gate electrode structures to contact the doped region; and
first and second sidewall spacer structures disposed along outer sidewalls of the first and second gate electrode structures, respectively, and having a layer defining first and second outer sidewalls, respectively, adjacent to the contact; and
wherein the layer defining the first outer sidewall includes at least three indentations along the first outer sidewall facing a first side of the contact.
13 . The integrated circuit of claim 12 , wherein the second outer sidewall includes at least two indentations along the second outer sidewall facing a second side of the contact.
14 . The integrated circuit of claim 13 , wherein the at least three indentations along the first outer sidewall are mirrored by at least three indentations along the second outer sidewall.
15 . The integrated circuit of claim 14 , wherein the first and second sidewall spacer structures comprise:
a first conformal layer comprising a base portion and a collar portion extending upward from the base portion, the base portion and the collar portion each laterally surrounding the first gate electrode structure, wherein the base portion is wider than the collar portion such that an upper surface of the base portion corresponds to a ledge; and
a second conformal layer extending over an upper surface of the first conformal layer and extending laterally over the upper surface of the first conformal layer over the first gate electrode structure.
16 . The integrated circuit of claim 15 , wherein the collar portion has a thickness between its sidewalls and wherein nearest outer sidewalls of the first and second gate electrode structures are separated by a lateral spacing, wherein a ratio of the thickness to the lateral spacing ranges from 1:20 to 3:20.
17 . An integrated circuit, comprising:
a substrate;
first and second channel regions disposed in the substrate, the first and second channel regions having a first conductivity type;
a common source/drain region disposed in the substrate between the first and second channel regions, the common source/drain region having a second conductivity type opposite the first conductivity type;
first and second gate electrode structures disposed over the first and second channel regions, respectively;
a dielectric layer overlying the first and second gate electrode structures;
a contact extending through the dielectric layer between nearest neighboring sidewalls of the first and second gate electrode structures to contact the common source/drain region; and
first and second sidewall spacer structures disposed along outer sidewalls of the first and second gate electrode structures, respectively, and having a material defining first and second outer sidewalls of the first and second sidewall spacer structures facing the contact, wherein the material defining the first outer sidewall includes at least three indentations in the first outer sidewall.
18 . The integrated circuit of claim 17 ,
wherein the second outer sidewall includes at least two indentations along the second outer sidewall facing a second side of the contact.
19 . The integrated circuit of claim 18 , wherein a plane extends down a central axis of the contact, and wherein the at least two indentations along the first outer sidewall are mirrored by at least two indentations along the second outer sidewall about the central axis.
20 . The integrated circuit of claim 19 , wherein the first and second sidewall spacer structures include a first conformal layer comprising a base portion and a collar portion extending upward from the base portion, the base portion and the collar portion each laterally surrounding the first gate electrode structure, wherein the base portion is wider than the collar portion such that an upper surface of the base portion corresponds to a ledge.