Semiconductor device and imaging device
The present technology relates to a semiconductor device and an imaging device capable of efficiently dissipating heat generated in a semiconductor package including a resin. A first substrate, a second substrate, a wiring layer that is located between the first substrate and the second substrate, and a slit that penetrates the first substrate and reaches the wiring layer are provided. The gap is provided for each wiring provided in the wiring layer. The present technology can be applied to, for example, a semiconductor device in which a chip on which an imaging element is formed and a chip that processes a signal from the imaging element are stacked.
1 . A semiconductor device, comprising:
a first substrate;
a second substrate;
a wiring layer that is located between the first substrate and the second substrate; and
a slit that penetrates the first substrate and reaches the wiring layer, wherein the wiring layer has a gap connected to the slit.
2 . The semiconductor device according to claim 1 , wherein the gap is provided for each wiring provided in the wiring layer.
3 . The semiconductor device according to claim 1 , wherein the gap includes a plurality of wirings provided in the wiring layer.
4 . The semiconductor device according to claim 1 , wherein the gap is provided in entirety of a region where a wiring is formed in the wiring layer.
5 . The semiconductor device according to claim 1 , wherein a wiring provided in the wiring layer is connected to an electrode that penetrates the first substrate.
6 . The semiconductor device according to claim 1 , wherein a shape of the slit is any of a linear shape, a polygonal shape, and a circular shape.
7 . The semiconductor device according to claim 1 ,
wherein a first chip including the first substrate and a second chip including the second substrate are stacked,
the wiring layer is a layer in which a first wiring layer included in the first chip and a second wiring layer included in the second chip are connected, and
a first wiring formed in the first wiring layer is located in the gap.
8 . The semiconductor device according to claim 7 , wherein also a second wiring formed in the second wiring layer is located in the gap.
9 . The semiconductor device according to claim 7 , wherein the second chip is a solid-state imaging element.
10 . The semiconductor device according to claim 1 , wherein a wiring located in the gap is a dummy wiring.
11 . A semiconductor device, comprising:
a first substrate;
a second substrate;
a wiring layer that is located between the first substrate and the second substrate; and
a slit that penetrates the first substrate and reaches the wiring layer, wherein a wiring located in a gap is a dummy wiring.
12 . The semiconductor device according to claim 11 , wherein the dummy wiring is connected to an electrode that penetrates the first substrate.
13 . The semiconductor device according to claim 11 , wherein a wiring provided in the wiring layer is connected to an electrode that penetrates the first substrate.
14 . The semiconductor device according to claim 11 , wherein a shape of the slit is any of a linear shape, a polygonal shape, and a circular shape.
15 . The semiconductor device according to claim 11 ,
wherein a first chip including the first substrate and a second chip including the second substrate are stacked,
the wiring layer is a layer in which a first wiring layer included in the first chip and a second wiring layer included in the second chip are connected, and
a first wiring formed in the first wiring layer is located in the gap.
16 . A semiconductor device, comprising:
a first substrate;
a second substrate;
a wiring layer that is located between the first substrate and the second substrate; and
a slit that penetrates the first substrate and reaches the wiring layer,
wherein a first chip including the first substrate and a second chip including the second substrate are stacked,
the wiring layer is a layer in which a first wiring layer included in the first chip and a second wiring layer included in the second chip are connected, and
a first wiring formed in the first wiring layer is located in a gap.
17 . The semiconductor device according to claim 16 , wherein also a second wiring formed in the second wiring layer is located in the gap.
18 . The semiconductor device according to claim 16 , wherein the second chip is a solid-state imaging element.
19 . The semiconductor device according to claim 16 , wherein a shape of the slit is any of a linear shape, a polygonal shape, and a circular shape.
20 . An imaging device, comprising:
a first chip on which a solid-state imaging element is formed;
a second chip that processes a signal from the first chip;
a wiring layer in which a first wiring layer included in the first chip and a second wiring layer included in the second chip are connected;
a gap that is provided in part of the wiring layer; and
a slit that penetrates the second chip connected to the gap.