Display panel and manufacturing method therefor, and display apparatus

1 . A display panel, comprising a display area and a peripheral area located outside the display area, wherein the peripheral area comprises a binding area located on one side of the display area along a column direction, and the display panel comprises:

a driving backplane comprising a substrate, a pixel circuit layer and a first planar layer stacked in sequence;

wherein the pixel circuit layer comprises a plurality of pixel circuits, a plurality of data wiring lines and a plurality of data transfer lines, one column of the pixel circuits is connected to one of the data wiring lines, at least part of the pixel circuits located in the display area form a plurality of pixel circuit islands distributed in an array, a plurality of the data transfer lines are located in the display area and do not overlap with the pixel circuit islands, one end of one of the data transfer lines is connected to one of the data wiring lines in the display area, and other end is extended to the binding area;

a plurality of first via holes connected to the plurality of pixel circuits in one-to-one correspondence are disposed in the first planar layer;

a transfer layer, located on a side of the first planar layer away from the substrate, and comprising a first transfer line;

a second planar layer, located on a side of the transfer layer away from the substrate, and provided with a plurality of second via holes corresponding to the plurality of first via holes in one-to-one correspondence, wherein the plurality of pixel circuit islands comprises a first pixel circuit, and two ends of the first transfer line are respectively connected to the first via hole and the second via hole corresponding to the first pixel circuit; and

a light-emitting layer, located on a side of the second planar layer away from the substrate, and comprising a plurality of light-emitting units connected to the plurality of second via holes in one-to-one correspondence, wherein light-emitting areas of the light-emitting units are not overlapped with the second via holes, the plurality of light-emitting units comprises a first light-emitting unit, and the light-emitting area of the first light-emitting unit has an overlapping portion with the first via hole corresponding to the first pixel circuit;

wherein the plurality of pixel circuit islands comprises a second pixel circuit; and wherein the light-emitting areas of the plurality of light-emitting units do not overlap with the first via hole corresponding to the second pixel circuit, and the first via hole corresponding to the second pixel circuit has an overlapping portion with the corresponding second via hole.

2 . The display panel according to claim 1 , wherein the plurality of pixel circuit islands comprises a second pixel circuit, and the transfer layer further comprises a second transfer line; and

wherein the light-emitting areas of the plurality of light-emitting units do not overlap with the first via hole corresponding to the second pixel circuit, the first via hole corresponding to the second pixel circuit do not overlap with the corresponding second via hole, and two ends of the second transfer line are respectively connected to the first via hole and the second via hole corresponding to the second pixel circuit.

3 . The display panel according to claim 1 , wherein the transfer layer comprises multiple layers of transfer sub-layers and an interlayer insulating layer located between any two adjacent transfer sub-layers; and

the multiple transfer sub-layers each comprises a first transfer sub-line, and the interlayer insulating layer comprises a via hole, and the via hole is connected to the first transfer sub-lines of the transfer sub-layers located on both sides, and the multiple first transfer sub-lines are connected in sequence to form the first transfer line.

4 . The display panel according to claim 1 , wherein the pixel circuit layer comprises a transistor layer, a first source-drain metal layer, a third planar layer and a second source-drain metal layer sequentially stacked in a direction away from the substrate;

the second source-drain metal layer comprises a plurality of pairs of power wirings arranged along a row direction and extended along the column direction, each pair of the power wirings forms a plurality of avoidance areas, and the second source-drain metal layer further comprises a pair of transfer electrodes located in the avoidance area and extended along the column direction, the plurality of transfer electrodes comprises a first transfer electrode corresponding to the first pixel circuit, and the first transfer electrode is connected to the first source-drain metal layer and a first end of the first transfer line respectively; and

the light-emitting layer further comprises a pixel definition layer provided on a surface of the first planar layer away from the substrate, the pixel definition layer is provided with pixel openings corresponding to the plurality of the light-emitting units in one-to-one correspondence, each light-emitting unit comprises a first electrode, an organic light-emitting layer and a second electrode sequentially stacked on one side in a direction away from the second planar layer, the first electrode comprises an exposed area exposed at a corresponding pixel opening and a covered area covered by the pixel definition layer, the exposed area of the first electrode forms a light-emitting area of the corresponding light-emitting unit, and a second end of the first transfer line is connected to the covered area of the light-emitting unit.

5 . The display panel according to claim 4 , wherein the first transfer line is extended along the row direction, and the first end of the first transfer line has an overlapping portion with at least a part of the first transfer electrode, the first via hole corresponding to the first pixel circuit and the exposed area of the first light-emitting unit, and the second end of the first transfer line has an overlapping portion with the second via hole corresponding to the first pixel circuit and the covered area of the light-emitting unit.

6 . The display panel according to claim 4 , wherein the first transfer line is extended along the row direction, and the first end of the first transfer line has an overlapping portion with at least a part of the first transfer electrode, the first via hole corresponding to the first pixel circuit and the exposed area of the first light-emitting unit, the second end of the first transfer line has an overlapping portion with the second via hole corresponding to the first pixel circuit and the covered area of a second light-emitting unit among the plurality of light-emitting units, and the second light-emitting unit is adjacent to the first light-emitting unit.

7 . The display panel according to claim 4 , wherein the transfer layer further comprises a second transfer line, and the plurality of transfer electrodes comprises a second transfer electrode corresponding to the second pixel circuit;

at least part of the second transfer electrode is overlapped with the first via hole corresponding to the second pixel circuit, and is not overlapped with the exposed areas of the plurality of light-emitting units; and

the second transfer line is extended along the row direction, a first end of the second transfer line has an overlapping portion with at least part of the second transfer electrode, and a second end of the second transfer line has an overlapping portion with the second via hole corresponding to the second pixel circuit and the covered area of a third light-emitting unit among the plurality of light-emitting units.

8 . The display panel according to claim 4 , wherein the data transfer line comprises a first segment of wiring and a second segment of wiring;

the first segment of wiring is extended along the row direction, the second segment of wiring is extended along the column direction, one end of the first segment of wiring is connected to a data wiring, other end of the first segment of wiring is connected to one end of the second segment of wiring, and other end of the second segment of wiring is extended to the binding area; and

first segment of wirings and part of the second segment of wirings of the plurality of data transfer lines are located on the first source-drain metal layer, and remaining second segment of wirings of the plurality of data transfer lines are located on the second source-drain metal layer.

9 . The display panel according to claim 1 , wherein the pixel circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and a storage capacitor;

a control electrode of the first transistor is used to load a capacitor reset control signal, a first electrode of the first transistor is used to load an initial voltage signal, and a second electrode of the first transistor is connected to a first electrode of the second transistor, a control electrode of the third transistor, and one end of the storage capacitor;

a control electrode of the second transistor is used to load a first scan signal, and a second electrode of the second transistor is connected to a first electrode of the third transistor and a first electrode of the sixth transistor;

a second electrode of the third transistor is connected to a first electrode of the fourth transistor and a first electrode of the fifth transistor, a control electrode of the fourth transistor is used to load a second scan signal, a second electrode of the fourth transistor is used to load a driving data signal, a control electrode of the fifth transistor is used to load an enable signal, a second electrode of the fifth transistor is connected to other end of the storage capacitor, and is used to load a power supply voltage signal; and

a control electrode of the sixth transistor is used to the an enable signal, a second electrode of the sixth transistor is connected to a first electrode of the seventh transistor and is used to connect to the corresponding light-emitting unit, a control electrode of the seventh transistor is used to load an electrode reset control signal, and a second electrode of the seventh transistor is used to load the initial voltage signal.

10 . The display panel according to claim 9 , wherein the pixel circuit layer comprises a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layers and a source-drain metal layer;

the first semiconductor layer comprises an active layer of each of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor, and the second semiconductor layer comprises an active layer of each of the first transistor and the second transistor;

the first gate metal layer is provided with a first scan line and an enable signal line extending along the row direction and sequentially arranged along the column direction, and first electrode plates located between the first scan line and the enable signal line and spaced apart along the row direction, the first scan line is used to load the first scan signal, and the enable signal line is used to load the enable signal;

the second gate metal layer is provided with an initial voltage wiring, a first reset control line and a second scan wiring extending along the row direction and sequentially arranged along the column direction, and second electrode plates located at a side of the second scan wiring away from the first reset control line and spaced apart along the row direction, the initial voltage wiring is used to load the initial voltage signal, the first reset control line is used to load the capacitor reset control signal, and the second scan line is used to load the second scan signal;

the third gate metal layer is provided with a second reset control line and a third scan line extending along the row direction and sequentially arranged along the column direction, the second reset control line is used to load the electrode reset control signal, and the third scan line is used to load the second scan signal;

the initial voltage wiring and the first reset control line are located on a side of the first scan wiring away from the enable signal line, the second scan wiring and the second electrode plate are located between the first scan wiring and the enable signal line, and the second plate has an overlapping portion with the first plate, the second reset control line is located between the initial voltage wiring and the first scan line, and has an overlapping portion with the first reset control line, and the third scan line is located between the first scan line and the second electrode and has an overlapping portion with the second scan wiring; and

the transfer layer comprises the transfer line extending along the row direction, and the transfer line corresponding to a previous row of pixel circuits in two adjacent rows of pixel circuits in the pixel circuit island is located on a side of the enable signal line close to the second electrode plate, and has an overlapping portion with the second electrode plate, and the transfer line corresponding to a next row of pixel circuits is located on a side of the enable signal line away from the second electrode plate.

11 . The display panel according to claim 1 , wherein the display area comprises a transparent display area and a normal display area located at the periphery of the transparent display area; and

a distribution density of the pixel circuits in the transparent display area is smaller than the distribution density of the pixel circuits in the normal display area, the plurality of pixel circuits comprise a third pixel circuit located in the normal display area, the transfer layer further comprises a third transfer line, and two ends of the third transfer line are respectively connected to the third pixel circuit and one of the light-emitting units in the transparent display area.

12 . The display panel according to claim 1 , wherein the display area comprises a main display area and a secondary display area located on one side or both sides of the main display area along the row direction; and

the plurality of pixel circuit islands and the plurality of data transfer lines are located in the main display area, and one end of one of the data transfer lines is extended into the secondary display area and is connected to one of the data wirings, and other end is extended to the binding area.

13 . The display panel according to claim 1 , wherein the material of the first transfer line is a transparent conductive material.

14 . A method of manufacturing display panel, comprising:

forming a driving backplane, the driving backplane comprising a substrate, a pixel circuit layer and a first planar layer stacked in sequence;

wherein display panel comprises a display area and a peripheral area located outside the display area, wherein the peripheral area comprises a binding area located on one side of the display area along a column direction, the pixel circuit layer comprises a plurality of pixel circuits, a plurality of data wiring lines and a plurality of data transfer lines, one column of the pixel circuits is connected to one of the data wiring lines, at least part of the pixel circuits located in the display area form a plurality of pixel circuit islands distributed in an array, a plurality of the data transfer lines are located in the display area and do not overlap with the pixel circuit islands, one end of one of the data transfer lines is connected to one of the data wiring lines in the display area, and other end is extended to the binding area, and a plurality of first via holes connected to the plurality of pixel circuits in one-to-one correspondence are disposed in the first planar layer;

forming a transfer layer on a side of the first planar layer away from the substrate, the transfer layer comprising a first transfer line;

forming a second planar layer on a side of the transfer layer away from the substrate, wherein the second planar layer is provided with a plurality of second via holes corresponding to the plurality of first via holes in one-to-one correspondence, the plurality of pixel circuit islands comprises a first pixel circuit, and two ends of the first transfer line are respectively connected to the first via hole and the second via hole corresponding to the first pixel circuit; and

forming a light-emitting layer on a side of the second planar layer away from the substrate, the light-emitting layer comprising a plurality of light-emitting units connected to the plurality of second via holes in one-to-one correspondence, wherein light-emitting areas of the light-emitting units are not overlapped with the second via holes, the plurality of light-emitting units comprises a first light-emitting unit, and the light-emitting area of the first light-emitting unit has an overlapping portion with the first via hole corresponding to the first pixel circuit;

wherein the plurality of pixel circuit islands comprises a second pixel circuit; and wherein the light-emitting areas of the plurality of light-emitting units do not overlap with the first via hole corresponding to the second pixel circuit, and the first via hole corresponding to the second pixel circuit has an overlapping portion with the corresponding second via hole.

15 . A display device, comprising a display panel, the display panel comprising a display area and a peripheral area located outside the display area, wherein the peripheral area comprises a binding area located on one side of the display area along a column direction, and the display panel comprises:

a driving backplane comprising a substrate, a pixel circuit layer and a first planar layer stacked in sequence;

wherein the pixel circuit layer comprises a plurality of pixel circuits, a plurality of data wiring lines and a plurality of data transfer lines, one column of the pixel circuits is connected to one of the data wiring lines, at least part of the pixel circuits located in the display area form a plurality of pixel circuit islands distributed in an array, a plurality of the data transfer lines are located in the display area and do not overlap with the pixel circuit islands, one end of one of the data transfer lines is connected to one of the data wiring lines in the display area, and other end is extended to the binding area;

a plurality of first via holes connected to the plurality of pixel circuits in one-to-one correspondence are disposed in the first planar layer;

a transfer layer, located on a side of the first planar layer away from the substrate, and comprising a first transfer line;

a second planar layer, located on a side of the transfer layer away from the substrate, and provided with a plurality of second via holes corresponding to the plurality of first via holes in one-to-one correspondence, wherein the plurality of pixel circuit islands comprises a first pixel circuit, and two ends of the first transfer line are respectively connected to the first via hole and the second via hole corresponding to the first pixel circuit; and

a light-emitting layer, located on a side of the second planar layer away from the substrate, and comprising a plurality of light-emitting units connected to the plurality of second via holes in one-to-one correspondence, wherein light-emitting areas of the light-emitting units are not overlapped with the second via holes, the plurality of light-emitting units comprises a first light-emitting unit, and the light-emitting area of the first light-emitting unit has an overlapping portion with the first via hole corresponding to the first pixel circuit;

wherein the plurality of pixel circuit islands comprises a second pixel circuit; and

wherein the light-emitting areas of the plurality of light-emitting units do not overlap with the first via hole corresponding to the second pixel circuit, and the first via hole corresponding to the second pixel circuit has an overlapping portion with the corresponding second via hole.

16 . The display device according to claim 15 , wherein the plurality of pixel circuit islands comprises a second pixel circuit, and the transfer layer further comprises a second transfer line; and

wherein the light-emitting areas of the plurality of light-emitting units do not overlap with the first via hole corresponding to the second pixel circuit, the first via hole corresponding to the second pixel circuit do not overlap with the corresponding second via hole, and two ends of the second transfer line are respectively connected to the first via hole and the second via hole corresponding to the second pixel circuit.

17 . The display device according to claim 15 , wherein the transfer layer comprises multiple layers of transfer sub-layers and an interlayer insulating layer located between any two adjacent transfer sub-layers; and

the multiple transfer sub-layers each comprises a first transfer sub-line, and the interlayer insulating layer comprises a via hole, and the via hole is connected to the first transfer sub-lines of the transfer sub-layers located on both sides, and the multiple first transfer sub-lines are connected in sequence to form the first transfer line.

18 . The display device according to claim 15 , wherein the pixel circuit layer comprises a transistor layer, a first source-drain metal layer, a third planar layer and a second source-drain metal layer sequentially stacked in a direction away from the substrate;

the second source-drain metal layer comprises a plurality of pairs of power wirings arranged along a row direction and extended along the column direction, each pair of the power wirings forms a plurality of avoidance areas, and the second source-drain metal layer further comprises a pair of transfer electrodes located in the avoidance area and extended along the column direction, the plurality of transfer electrodes comprises a first transfer electrode corresponding to the first pixel circuit, and the first transfer electrode is connected to the first source-drain metal layer and a first end of the first transfer line respectively; and

the light-emitting layer further comprises a pixel definition layer provided on a surface of the first planar layer away from the substrate, the pixel definition layer is provided with pixel openings corresponding to the plurality of the light-emitting units in one-to-one correspondence, each light-emitting unit comprises a first electrode, an organic light-emitting layer and a second electrode sequentially stacked on one side in a direction away from the second planar layer, the first electrode comprises an exposed area exposed at a corresponding pixel opening and a covered area covered by the pixel definition layer, the exposed area of the first electrode forms a light-emitting area of the corresponding light-emitting unit, and a second end of the first transfer line is connected to the covered area of the light-emitting unit.