IP Library › Granted Patent US 12707840
Granted Patent B2
US 12707840 · App. 18/404,255 · Granted Aug 11, 2026

Display apparatus

Inventors: Minwoo Byun (Yongin-si, KR); Jihyun Ka (Yongin-si, KR); Chulkyu Kang (Yongin-si, KR); Wonkyu Kwak (Yongin-si, KR)
Assignee: SAMSUNG DISPLAY CO., LTD.
H10K59/131H10K59/1213H10K59/1216
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12707840
App. No.
18/404,255
Granted
Aug 11, 2026
Kind
B2
Abstract

Each pixel of a display apparatus includes a first transistor, a second transistor connected to a first gate of the first transistor and a data line, a third transistor connected to the first gate of the first transistor and a first voltage line, a first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor, and a second capacitor including a first electrode connected to the first voltage line and a second electrode connected to the second terminal of the first transistor. The first electrode of the second capacitor and the first voltage line are disposed on a same layer.

Claims (126)

1 . A display apparatus comprising:

a plurality of pixels,

wherein each of the plurality of pixels comprises:

a first transistor including a first terminal, a second terminal, a first gate, and a second gate connected to the second terminal;

a second transistor connected to the first gate of the first transistor and a data line;

a third transistor connected to the first gate of the first transistor and a first voltage line;

a fourth transistor connected to the first terminal of the first transistor and a second voltage line;

a first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor; and

a second capacitor including a first electrode connected to the first voltage line and a second electrode connected to the second terminal of the first transistor, and

the first electrode of the second capacitor and the first voltage line are disposed on a same layer.

2 . The display apparatus of claim 1 , wherein the second electrode of the second capacitor is connected to the second gate of the first transistor.

3 . The display apparatus of claim 1 , wherein

the first electrode of the first capacitor includes an upper electrode and a lower electrode,

the upper electrode and the first gate of the first transistor are disposed on a same layer,

the lower electrode and the first electrode of the second capacitor are disposed on a same layer, and

the lower electrode is connected to the upper electrode.

4 . The display apparatus of claim 1 , wherein during one frame, a gate signal is supplied to a gate of the third transistor once, and a gate signal is supplied to a gate of the fourth transistor two or more times.

5 . The display apparatus of claim 1 , wherein

each of the plurality of pixels further comprises:

a fifth transistor connected to the second terminal of the first transistor and a third voltage line;

a sixth transistor connected to the second terminal of the first transistor and a light-emitting diode; and

a seventh transistor connected to the light-emitting diode and a fourth voltage line, and

a same gate signal is supplied to a gate of the fifth transistor and a gate of the seventh transistor.

6 . The display apparatus of claim 5 , wherein a timing at which a gate signal is applied to the gate of the fourth transistor precedes a timing at which a gate signal is applied to the gate of the sixth transistor.

7 . The display apparatus of claim 1 , wherein

each of the plurality of pixels further comprises:

a fifth transistor connected to the second terminal of the first transistor and a third voltage line;

a sixth transistor connected to the second terminal of the first transistor and a light-emitting diode; and

a seventh transistor connected to the light-emitting diode and a fourth voltage line, and

a gate signal supplied to a gate of the fifth transistor and a gate signal supplied to a gate of the seventh transistor are different.

8 . The display apparatus of claim 7 , wherein during one frame, a gate signal is supplied to a gate of the fifth transistor once, and a gate signal is supplied to a gate of the seventh transistor two or more times.

9 . The display apparatus of claim 1 , wherein

one frame includes a first scan period including a first non-emission period and a first emission period and a second scan period including a second non-emission period and a second emission period,

each of the plurality of pixels further comprises a fifth transistor connected to the second terminal of the first transistor and a third voltage line, and

the first non-emission period comprises:

a writing period in which a first gate signal is applied to a gate of the second transistor;

a first period in which a second gate signal is applied to a gate of the fifth transistor and a third gate signal is applied to a gate of the third transistor, before the writing period; and

a second period in which the third gate signal is applied to a gate of the third transistor and a fourth gate signal is applied to a gate of the fourth transistor, between the writing period and the first period.

10 . The display apparatus of claim 9 , wherein the second non-emission period comprises a third period in which the second gate signal is applied to the gate of the fifth transistor.

11 . A display apparatus comprising:

a plurality of pixels,

wherein each of the plurality of pixels comprises:

a first transistor including a first terminal, a second terminal, a first gate, and a second gate connected to the second terminal;

a second transistor connected to the first gate of the first transistor and a data line;

a third transistor connected to the first gate of the first transistor and a first voltage line;

a fourth transistor connected to the first terminal of the first transistor and a second voltage line;

a fifth transistor connected to the second terminal of the first transistor and a light-emitting diode;

a first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor; and

a second capacitor including a first electrode connected to the first voltage line and a second electrode connected to the second terminal of the first transistor, and

a timing at which a gate signal is applied to a gate of the fourth transistor precedes a timing at which a gate signal is applied to a gate of the fifth transistor.

12 . The display apparatus of claim 11 , wherein the second electrode of the second capacitor is connected to the second gate of the first transistor.

13 . The display apparatus of claim 11 , wherein

the first electrode of the first capacitor includes an upper electrode and a lower electrode,

the upper electrode and the first gate of the first transistor are disposed on a same layer,

the lower electrode and the first electrode of the second capacitor are disposed on a same layer, and

the lower electrode is connected to the upper electrode.

14 . The display apparatus of claim 11 , wherein during one frame, a gate signal is supplied to a gate of the third transistor once, and a gate signal is supplied to a gate of the fourth transistor two or more times.

15 . The display apparatus of claim 11 , wherein

each of the plurality of pixels further comprises:

a sixth transistor connected to the second terminal of the first transistor and a third voltage line; and

a seventh transistor connected to the light-emitting diode and a fourth voltage line, and

a same gate signal is supplied to a gate of the sixth transistor and a gate of the seventh transistor.

16 . The display apparatus of claim 11 , wherein each of the plurality of pixels further comprises:

a sixth transistor connected to the second terminal of the first transistor and a third voltage line; and

a seventh transistor connected to the light-emitting diode and a fourth voltage line, and

a gate signal supplied to a gate of the sixth transistor and a gate signal supplied to a gate of the seventh transistor are different.

17 . The display apparatus of claim 16 , wherein during one frame, a gate signal is supplied to a gate of the sixth transistor once, and a gate signal is supplied to a gate of the seventh transistor two or more times.

18 . A display apparatus comprising:

a plurality of pixels,

wherein each of the plurality of pixels comprises:

a first transistor including a first terminal, a second terminal, a first gate, and a second gate connected to the second terminal;

a second transistor connected to the first gate of the first transistor and a data line;

a third transistor connected to the first gate of the first transistor and a first voltage line;

a fourth transistor connected to the first terminal of the first transistor and a second voltage line;

a first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor;

a second capacitor including a first electrode connected to the second voltage line and a second electrode connected to the second terminal of the first transistor; and

a third capacitor including a first electrode connected to the second terminal of the first transistor and a second electrode connected to one electrode of a light-emitting diode.

19 . The display apparatus of claim 18 , wherein

each of the plurality of pixels further comprises:

a fifth transistor connected to the second terminal of the first transistor and a third voltage line;

a sixth transistor connected to the second terminal of the first transistor and the light-emitting diode; and

a seventh transistor connected to the light-emitting diode and a fourth voltage line,

a same gate signal is supplied to a gate of the fifth transistor and a gate of the seventh transistor, and

a timing at which a gate signal is applied to a gate of the fourth transistor precedes a timing at which a gate signal is applied to a gate of the sixth transistor.

20 . The display apparatus of claim 18 , wherein

each of the plurality of pixels further comprises:

a fifth transistor connected to the second terminal of the first transistor and a third voltage line;

a sixth transistor connected to the second terminal of the first transistor and the light-emitting diode; and

a seventh transistor connected to the light-emitting diode and a fourth voltage line,

a gate signal supplied to a gate of the fifth transistor and a gate signal supplied to a gate of the seventh transistor are different, and

a timing at which a gate signal is applied to a gate of the fourth transistor precedes a timing at which a gate signal is applied to a gate of the sixth transistor.

21 . A display apparatus comprising:

a plurality of pixels,

wherein each of the plurality of pixels comprises:

a first transistor including a first terminal, a second terminal, a first gate, and a second gate connected to the second terminal;

a second transistor connected to the first gate of the first transistor and a data line;

a third transistor connected to the first gate of the first transistor and a first voltage line;

a fourth transistor connected to the first terminal of the first transistor and a second voltage line;

a fifth transistor connected to the second terminal of the first transistor and a first electrode of a light-emitting diode;

a first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor; and

a second capacitor including a first electrode connected to the second terminal of the first transistor and a second electrode connected to a second electrode of the light-emitting diode.

22 . The display apparatus of claim 21 , wherein the first electrode of the second capacitor is connected to the second gate of the first transistor.

23 . The display apparatus of claim 21 , wherein

the first electrode of the first capacitor includes an upper electrode and a lower electrode,

the upper electrode and the first gate of the first transistor are disposed on a same layer,

the lower electrode and the first electrode of the second capacitor are disposed on a same layer, and

the lower electrode is connected to the upper electrode.

24 . The display apparatus of claim 21 , wherein during one frame, a gate signal is supplied to a gate of the third transistor once, and a gate signal is supplied to a gate of the fourth transistor two or more times.

25 . The display apparatus of claim 21 , wherein

each of the plurality of pixels further comprises:

a sixth transistor connected to the second terminal of the first transistor and a third voltage line; and

a seventh transistor connected to the first electrode of the light-emitting diode and a fourth voltage line, and

a same gate signal is supplied to a gate of the sixth transistor and a gate of the seventh transistor.

26 . The display apparatus of claim 21 , wherein a timing at which a gate signal is applied to a gate of the fourth transistor precedes a timing at which a gate signal is applied to a gate of the fifth transistor.

27 . The display apparatus of claim 21 , wherein each of the plurality of pixels further comprises:

a sixth transistor connected to the second terminal of the first transistor and a third voltage line; and

a seventh transistor connected to the first electrode of the light-emitting diode and a fourth voltage line, and

a gate signal supplied to a gate of the sixth transistor and a gate signal supplied to a gate of the seventh transistor are different.

28 . The display apparatus of claim 27 , wherein during one frame, a gate signal is supplied to a gate of the sixth transistor once, and a gate signal is supplied to a gate of the seventh transistor two or more times.

29 . The display apparatus of claim 21 , wherein one frame includes a first scan period including a first non-emission period and a first emission period and a second scan period including a second non-emission period and a second emission period,

each of the plurality of pixels further comprises a sixth transistor connected to the second terminal of the first transistor and a third voltage line, and

the first non-emission period comprises:

a writing period in which a first gate signal is applied to a gate of the second transistor;

a first period in which a second gate signal is applied to a gate of the sixth transistor and a third gate signal is applied to a gate of the third transistor, before the writing period; and

a second period in which the third gate signal is applied to a gate of the third transistor and a fourth gate signal is applied to a gate of the fourth transistor, between the writing period and the first period.

30 . The display apparatus of claim 29 , wherein the second non-emission period comprises a third period in which the second gate signal is applied to the gate of the sixth transistor.