Resistive random-access memory device
A RRAM (resistive random-access memory) device includes a bottom electrode line directly on a first metal structure, a top electrode island disposed beside the bottom electrode line, a resistive material sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island, and a cap layer covering a portion of the first metal structure and under the bottom electrode line.
1 . A resistive random-access memory (RRAM) device, comprising:
a bottom electrode line directly on a first metal structure;
a top electrode island disposed beside the bottom electrode line;
a resistive material sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island; and
a cap layer covering a portion of the first metal structure and under the bottom electrode line.
2 . The resistive random-access memory (RRAM) device according to claim 1 , further comprising a dielectric layer disposed on the bottom electrode lines, wherein the resistive material penetrates through the dielectric layer.
3 . The resistive random-access memory (RRAM) device according to claim 2 , wherein the dielectric layer comprises a silicon nitride layer.
4 . The resistive random-access memory (RRAM) device according to claim 1 , wherein the resistive material comprises transition-metal-oxide (TMO).
5 . The resistive random-access memory (RRAM) device according to claim 1 , wherein the resistive material has a U-shape cross-sectional profile.
6 . The resistive random-access memory (RRAM) device according to claim 1 , wherein the top electrode island has an I-shape cross-sectional profile or a T-shape cross-sectional profile.
7 . The resistive random-access memory (RRAM) device according to claim 2 , further comprising a second metal structure directly contacting the resistive material and the top electrode island.
8 . The resistive random-access memory (RRAM) device according to claim 7 , wherein the second metal structure comprises a first metal line and a second metal line disposed beside the first metal line.
9 . The resistive random-access memory (RRAM) device according to claim 8 , further comprising a via disposed beside the RRAM cell, wherein the via contacts the second metal line of the second metal structure directly.
10 . The resistive random-access memory (RRAM) device according to claim 7 , further comprising a second dielectric layer disposed on the dielectric layer, wherein the second metal structure disposed in the second dielectric layer.
11 . The resistive random-access memory (RRAM) device according to claim 2 , further comprising an inter-dielectric layer disposed beside the bottom electrode lines and the dielectric layer.
12 . The resistive random-access memory (RRAM) device according to claim 11 , wherein a top surface of the inter-dielectric layer is lower than a top surface of the dielectric layer.
13 . The resistive random-access memory (RRAM) device according to claim 1 , wherein a top surface of the cap layer is aligned with a bottom surface of the resistive material.
14 . The resistive random-access memory (RRAM) device according to claim 1 , wherein a top surface of the cap layer is higher than a bottom surface of the resistive material.
15 . The resistive random-access memory (RRAM) device according to claim 1 , wherein the resistive material penetrates through the cap layer.
16 . The resistive random-access memory (RRAM) device according to claim 1 , wherein a width of the cap layer is wider than a width of the resistive material.