Method of manufacturing semiconductor devices including a cap insulating layer
In method of manufacturing a semiconductor device, an opening is formed over a first conductive layer in a dielectric layer, a second conductive layer is formed over the first conductive layer in the opening without forming the second conductive layer on at least an upper surface of the dielectric layer, a third conductive layer is formed over the second conductive layer in the opening without forming the third conductive layer on at least an upper surface of the dielectric layer, and an upper layer is formed over the third conductive layer in the opening.
1 . A method of manufacturing a semiconductor device, comprising:
forming a gate space in a dielectric layer by removing a sacrificial gate electrode;
forming a gate dielectric layer in the gate space;
forming at least three conductive layers on the gate dielectric layer to fully fill the gate space;
recessing the gate dielectric layer and the at least three conductive layers to form recessed conductive layers,
wherein the at least three conductive layers are recessed to a substantially same height;
forming a first cap metal layer on the recessed conductive layers in the gate space without forming the first cap metal layer on an upper surface of the dielectric layer; and
forming a cap insulating layer over the first cap metal layer in the gate space,
wherein the cap insulating layer is separated from the recessed conductive layers by the first cap metal layer.
2 . The method of claim 1 , wherein:
at least one of the conductive layers has a U-shape cross section, and
the first cap metal layer does not have a U-shape cross section.
3 . The method of claim 1 , wherein at least one of the conductive layers does not have a U-shape cross section and includes TiN or WCN.
4 . The method of claim 1 , wherein the first cap metal layer is formed by an atomic layer deposition using a metal penta-chloride as a source gas.
5 . The method of claim 4 , further comprising, before the cap insulating layer is formed, forming a second cap metal layer on the first cap metal layer in the gate space without forming the second cap metal layer on the upper surface of the dielectric layer.
6 . The method of claim 5 , wherein gate sidewall spacers are disposed on opposing sidewalls of the conductive layers as seen in cross section.
7 . The method of claim 6 , wherein the second cap metal layer covers tops of the gate sidewall spacers.
8 . The method of claim 1 , wherein the gate cap insulating layer includes one or more of silicon nitride, SiON, and SiOCN.
9 . The method of claim 1 , wherein forming the at least three conductive layers comprises:
forming a first conductive layer on the gate dielectric layer;
forming a second conductive layer on the first conductive layer; and
forming a third conductive layer on the second conductive layer,
wherein the first, second, and third conductive layers are made of different materials.
10 . The method of claim 1 , wherein one or more fin structures are disposed in the gate space.
11 . A method of manufacturing a semiconductor device, comprising:
forming an opening in a dielectric layer by removing a sacrificial gate electrode;
forming a gate dielectric layer in the opening;
forming a barrier layer over the gate dielectric layer;
forming a work function adjustment material layer over the barrier layer;
forming a blocking metal layer over the work function adjustment material layer over to fully fill the opening;
recessing the gate dielectric layer, barrier layer, work function adjustment material layer, and the blocking metal layer to form a recess in the dielectric layer,
wherein the barrier layer, work function adjustment material layer, and the blocking metal layer are recessed to a substantially same height;
forming a first cap metal layer in the recess without forming the first cap metal layer on an upper surface of the dielectric layer; and
forming a cap insulating layer over the first cap metal layer in the recess,
wherein the cap insulating layer is separated from the recessed gate dielectric layer, barrier layer, work function adjustment material layer, and blocking metal layer by the first cap metal layer.
12 . The method of claim 11 , wherein:
at least one of the barrier layer and the work function adjustment material layer has a U-shape cross section, and
the first cap metal layer does not have a U-shape cross section.
13 . The method of claim 11 , wherein the blocking metal layer includes one or more of Ta, TaN, Ti, TiN, or TiSiN.
14 . The method of claim 11 , wherein the first cap metal layer is formed by an atomic layer deposition using a metal penta-chloride as a source gas.
15 . The method of claim 11 , further comprising, before the cap insulating layer is formed, forming a second cap metal layer on the first cap metal layer in the recess without forming the second cap metal layer on the upper surface of the dielectric layer.
16 . A method of manufacturing a semiconductor device, comprising:
forming an opening in a dielectric layer by removing a sacrificial gate electrode;
forming a gate dielectric layer in the opening;
forming a first conductive layer over the gate dielectric layer;
forming a second conductive layer over the first conductive layer;
recessing the first conductive layer and the second conductive layer to expose a portion of the gate dielectric layer;
forming a third conductive layer over the recessed second conductive layer and the exposed portion of the gate dielectric layer;
forming a fourth conductive layer over the third conductive layer to fully fill the opening;
recessing the gate dielectric layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer to form a recess in the dielectric layer,
wherein the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer are recessed to a substantially same height;
forming a first cap metal layer in the recess without forming the first cap metal layer on an upper surface of the dielectric layer; and
forming a cap insulating layer over the first cap metal layer in the recess,
wherein the cap insulating layer is separated from the recessed gate dielectric layer, first conductive layer, second conductive layer, third conductive layer, and the fourth conductive layer by the first cap metal layer.
17 . The method of claim 16 , wherein:
at least one of the first conductive layer, the second conductive layer, and the third conductive layer has a U-shape cross section, and
the first cap metal layer does not have a U-shape cross section.
18 . The method of claim 16 , wherein the fourth conductive layer includes one or more of Ta, TaN, Ti, TiN, or TiSiN.
19 . The method of claim 16 , wherein the first cap metal layer is formed by an atomic layer deposition using a metal penta-chloride as a source gas.
20 . The method of claim 16 , further comprising, before the cap insulating layer is formed, forming a second cap metal layer on the first cap metal layer in the recess without forming the second cap metal layer on the upper surface of the dielectric layer.