Plasma diced wafers and methods thereof

1 . A method of forming devices comprising:

providing a processed wafer comprising a plurality of dies formed thereon, wherein the processed wafer comprises

a wafer with active and inactive major wafer surfaces, wherein the active wafer includes circuit components of the devices,

a BEOL (back-end-of-line) dielectric disposed on the active major wafer surface with the circuit components, the BEOL dielectric includes interconnects interconnecting the circuit components,

a passivation layer disposed on a top surface of the BEOL dielectric, and

dicing channels separating the plurality of dies in x and y directions;

attaching a die attach film (DAF) on the inactive major wafer surface of the wafer;

attaching a backgrinding (BG) tape to a top surface of the passivation layer

stealth dicing the wafer to form a modified layer with cracks in the dicing channels in a lower portion from the inactive major wafer surface of the wafer;

mounting the processed wafer with a dicing tape on a wafer frame assembly;

removing the BG tape after stealth dicing the wafer;

patterning the passivation layer to form a patterned passivation layer, the patterned passivation layer exposes the dicing channels of the processed wafer;

plasma dicing partially the processed wafer using the patterned passivation layer as a plasma dicing mask, wherein the plasma dicing removes exposed dicing channels of the processed wafer until it reaches the lower portion of the wafer, leaving the lower portion of the wafer and the DAF remaining; and

performing a singulation process using lateral force to break the lower portion of the wafer and the DAF to singulate the processed wafer into individual devices, wherein the modified layer facilitates in singulating the processed wafer.

2 . The method of claim 1 wherein plasma dicing partially the processed wafer is performed after stealth dicing, and comprises

attaching the backgrinding (BG) tape to the top surface of the passivation layer; and

optionally backgrinding the inactive surface of the wafer to a desired thickness.

3 . The method of claim 2 comprises:

stealth dicing the wafer to form the modified layer from the inactive major wafer surface of the wafer;

attaching the DAF on the inactive major wafer surface of the wafer;

mounting the processed wafer with the dicing tape on the wafer frame assembly; and

removing the BG tape after stealth dicing the wafer.

4 . The method of claim 3 comprises:

patterning the passivation layer;

plasma dicing partially the processed wafer using the patterned passivation layer as a plasma dicing mask; and

performing the singulation process using lateral force to break the lower portion of the wafer and the DAF to singulate the processed wafer into individual devices.

5 . The method of claim 2 comprises:

attaching the DAF on the inactive major wafer surface of the wafer;

mounting the processed wafer with the dicing tape on the wafer frame assembly;

stealth dicing the wafer through the DAF and the dicing tape to form the modified layer from the inactive major wafer surface of the wafer.

6 . The method of claim 5 comprises:

removing the BG tape after stealth dicing the wafer;

patterning the passivation layer to form the patterned passivation layer, the patterned passivation layer exposes the dicing channels of the processed wafer;

plasma dicing partially the processed wafer using the patterned passivation layer as a plasma dicing mask; and

performing the singulation process using lateral force to break the lower portion of the wafer and the DAF to singulate the processed wafer into individual devices.

7 . The method of claim 1 wherein plasma dicing partially the processed wafer is performed prior to stealth dicing, and comprises:

mounting the processed wafer with the dicing tape on the wafer frame assembly;

patterning the passivation layer to form the patterned passivation layer; and

plasma dicing partially the processed wafer using the patterned passivation layer as a plasma dicing mask.

8 . The method of claim 7 comprises:

attaching the backgrinding (BG) tape to the top surface of the patterned passivation layer;

optionally backgrinding the inactive major wafer surface of the wafer to a desired thickness; and

removing the processed wafer from the dicing tape.

9 . The method of claim 8 comprises:

stealth dicing the wafer to form the modified layer with cracks in the lower portion of the wafer from the inactive major wafer surface of the wafer;

removing the BG tape from the processed wafer; and

performing the singulation process using lateral force to break the lower portion of the wafer and the DAF to singulate the processed wafer into individual devices.

10 . The method of claim 7 comprises:

attaching the backgrinding (BG) tape to the top surface of the patterned passivation layer;

optionally backgrinding the inactive major wafer surface of the wafer to a desired thickness;

removing the processed wafer from the dicing tape;

attaching the DAF on the inactive major wafer surface of the wafer;

mounting the processed wafer with the dicing tape on the wafer frame assembly;

stealth dicing the wafer through the DAF and dicing tape to form the modified layer from the inactive major wafer surface of the wafer;

removing the BG tape from the processed wafer, and

performing the singulation process using lateral force to break the lower portion of the wafer and the DAF to singulate the processed wafer into individual devices.

11 . The method of claim 4 wherein plasma dicing partially the processed wafer forms mask openings in the passivation stack with flat or chamfered sidewalls.

12 . The method of claim 11 wherein plasma dicing partially the processed wafer forms scalloped die sidewalls.

13 . The method of claim 6 wherein plasma dicing partially the processed wafer forms mask openings in the passivation stack with chamfered sidewalls.

14 . The method of claim 13 wherein plasma dicing partially the processed wafer forms scalloped die sidewalls.

15 . The method of claim 7 wherein plasma dicing partially the processed wafer forms mask openings in the passivation stack with chamfered sidewalls.

16 . The method of claim 15 wherein plasma dicing partially the processed wafer forms scalloped die sidewalls.