Structures for reducing gap fill defects in a vertically stacked semiconductor device and methods for forming the same
Vertically stacked semiconductor devices and methods of fabrication thereof that include a first semiconductor die bonded to a second device structure in a face-down configuration, a gap fill dielectric layer laterally surrounding the first semiconductor die, and a recess fill dielectric layer formed over the gap fill dielectric layer to fill concave recess defects in the gap fill dielectric that may result from cracks in the first semiconductor die. The recess fill dielectric layer may fill the entire volume of one or more concave recess defects in the gap fill dielectric material to a vertical depth of 5 μm or more below the backside surface of a semiconductor substrate of the first semiconductor die. Providing a recess fill dielectric layer within concave recess defects in the gap fill dielectric layer may result in enhanced protection against electrical arcing during subsequent processing steps and thereby provide improved device yields.
1 . A method of fabricating a vertically stacked semiconductor device, comprising:
bonding a first semiconductor die to a surface of a second device structure such that a backside surface of a first semiconductor substrate of the first semiconductor die faces away from the surface of the second device structure;
thinning the first semiconductor substrate of the first semiconductor die by removing a backside portion of the first semiconductor substrate;
forming a gap fill dielectric layer over the surface of the second device structure and laterally surrounding the first semiconductor die;
performing a planarization process on the gap fill dielectric layer, wherein following the planarization process the gap fill dielectric layer includes at least one concave recess defect; and
forming a recess fill dielectric layer within the at least one concave recess defect in the gap fill dielectric layer.
2 . The method of claim 1 , wherein:
the first semiconductor substrate is thinned by grinding the first semiconductor substrate to remove the backside portion of the first semiconductor substrate;
forming the gap fill dielectric layer comprises depositing a first dielectric material layer over the second device structure, side surfaces of the first semiconductor die and the backside surface of the first semiconductor substrate, and performing the planarization process comprises performing a first planarization process to remove portions of the first dielectric material from over the backside surface of the first semiconductor substrate; and
forming the recess fill dielectric layer comprises depositing a second dielectric material layer over the backside surface of the first semiconductor substrate and an upper surface of the gap fill dielectric layer, and performing a second planarization process to remove portions of the second dielectric material layer and provide a planar upper surface of the recess fill dielectric layer, wherein following the second planarization process, a vertical height of the planar upper surface of the recess fill dielectric layer is between 0 μm and 10 μm above the backside surface of the first semiconductor substrate.
3 . The method of claim 2 , wherein the first planarization process and the second planarization process comprise chemical mechanical planarization (CMP) processes.
4 . The method of claim 2 , wherein the recess fill dielectric layer is deposited via a selective oxidation.
5 . The method of claim 2 , wherein the recess fill dielectric layer comprises an organic dielectric material that is deposited by a spin coating process.
6 . The method of claim 5 , wherein the recess fill dielectric layer has a viscosity of 50 to 300 Pa·s and a filler content of 50 to 90% by weight.
7 . The method of claim 5 , wherein performing the second planarization process comprises performing an etching process to remove the organic dielectric material from over the backside surface of the first semiconductor substrate and the upper surface of the gap fill dielectric layer.
8 . The method of claim 2 , wherein the recess fill dielectric layer is deposited via a high-density plasma chemical vapor deposition (HDP-CVD) process.
9 . The method of claim 1 , wherein thinning the first semiconductor substrate of the first semiconductor die produces a crack in the first semiconductor substrate, wherein the gap fill dielectric layer partially fills a volume of the crack.
10 . The method of claim 9 , wherein a portion of the recess fill dielectric layer fills a remaining volume of the crack.
11 . The method of claim 10 , wherein the portion of the recess fill dielectric layer that fills the remaining volume of the crack is surrounded on a bottom surface and on side surfaces by the gap fill dielectric layer.
12 . The method of claim 11 , wherein the portion of the recess fill dielectric layer that fills the remaining volume of the crack is surrounded by the first semiconductor substrate on at least two sides.
13 . The method of claim 11 , wherein the bottom surface of the recess fill dielectric layer is located below a plane of the backside surface of the first semiconductor substrate by 5 μm or more.
14 . The method of claim 11 , wherein the portion of the recess fill dielectric layer that fills the remaining volume of the crack has a maximum width dimension of 10 μm or less.
15 . A method of fabricating a vertically stacked semiconductor device, comprising:
bonding a first semiconductor die to a surface of a second device structure such that a backside surface of a first semiconductor substrate of the first semiconductor die faces away from the surface of the second device structure;
grinding the first semiconductor substrate to remove a backside portion of the first semiconductor substrate, wherein grinding the first semiconductor substrate results in the formation of at least one crack in the first semiconductor substrate;
forming a gap fill dielectric layer over the surface of the second device structure and laterally surrounding the first semiconductor die;
planarizing the gap fill dielectric layer to provide a planar upper surface of the gap fill dielectric layer that includes a concave recess defect corresponding to a location of the crack in the first semiconductor substate; and
forming a recess fill dielectric layer over the gap fill dielectric layer and within the concave recess defect; and
planarizing the recess fill dielectric layer to provide a planar upper surface of the recess fill dielectric layer over the concave recess defect.
16 . The method of claim 15 , wherein grinding the first semiconductor substrate comprises reducing a thickness of the first semiconductor substrate from a first thickness of 500 μm to 800 μm to a second thickness of 50 μm to 100 μm.
17 . The method of claim 15 , wherein the first semiconductor die is bonded to the surface of the second device structure by a metal-to-metal and dielectric-to-dielectric direct bonding interface.
18 . A method of reducing gap fill defects in a vertically stacked semiconductor device, comprising:
providing a first semiconductor die bonded to a second device structure;
forming a gap fill dielectric layer laterally over an upper surface and side surfaces of the first semiconductor die;
planarizing the gap fill dielectric layer to remove the gap fill dielectric layer from over an upper surface of the first semiconductor die;
depositing an organic dielectric material over the gap fill dielectric layer and the upper surface of the first semiconductor die and within at least one concave recess defect in the gap fill dielectric layer; and
planarizing the organic dielectric material to provide a planar upper surface of the vertically stacked semiconductor device comprising the upper surface of the first semiconductor die, the upper surface of the gap fill dielectric layer, and an upper surface of the organic dielectric material.
19 . The method of claim 18 , wherein the organic dielectric material is deposited over the gap fill dielectric layer by spin-coating, and the method further comprises curing the organic dielectric material.
20 . The method of claim 18 , wherein the organic dielectric material comprises a molding underfill material.