IP Library › Granted Patent US 12707948
Granted Patent B2
US 12707948 · App. 17/338,958 · Granted Aug 11, 2026

Conductive via structures for gate contact or trench contact

Inventors: Leonard P. Guler (Hillsboro, OR); Tahir Ghani (Portland, OR); Charles H. Wallace (Portland, OR)
Assignee: Intel Corporation
H10W20/20H10D30/014H10D30/031H10D30/43H10D30/6735H10D30/6757H10D62/118H10D62/121H10D64/017H10D64/018H10P14/3462H10W20/0698H10W20/081H10W20/083H10D84/0147H10D84/0149H10D84/0184H10D84/0186
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Quick Facts
Patent No.
US 12707948
App. No.
17/338,958
Granted
Aug 11, 2026
Kind
B2
Abstract

Conductive via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures. A plurality of dielectric spacers has an uppermost surface co-planar with an uppermost surface of a plurality of gate structures and co-planar with an uppermost surface of a plurality of conductive trench contact structures. A dielectric layer is over the plurality of gate structures, over the plurality of conductive trench contact structures, and over the plurality of dielectric spacers. The dielectric layer has a planar uppermost surface. An opening is in the dielectric layer, the opening exposing one of the plurality of gate structures or one of the plurality of conductive trench contact structures. A conductive via is in the opening. The conductive via has an uppermost surface co-planar with the planar uppermost surface of the dielectric layer.

Claims (54)

1 . An integrated circuit structure, comprising:

a plurality of gate structures, each of the gate structures comprising a metal gate electrode;

a plurality of conductive trench contact structures alternating with the plurality of gate structures;

a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers has an uppermost surface co-planar with an uppermost surface of the metal gate electrodes of the plurality of gate structures and co-planar with an uppermost surface of the plurality of conductive trench contact structures;

a single dielectric layer over and in direct physical contact with the metal gate electrodes of the plurality of gate structures, over and in direct physical contact with the plurality of conductive trench contact structures, and over and in direct physical contact with the plurality of dielectric spacers, the single dielectric layer having a planar uppermost surface;

an opening in the single dielectric layer, the opening exposing one of the plurality of gate structures; and

a conductive via in the opening, the conductive via in direct physical contact with the one of the plurality of gate structures, and the conductive via having an uppermost surface co-planar with the planar uppermost surface of the single dielectric layer.

2 . The integrated circuit structure of claim 1 , wherein the opening extends into a portion of the one of the plurality of gate structures.

3 . The integrated circuit structure of claim 1 , wherein the plurality of gate structures is over one or more stacks of semiconductor nanowires.

4 . The integrated circuit structure of claim 1 , wherein the plurality of gate structures is over one or more stacks of semiconductor nanoribbons.

5 . The integrated circuit structure of claim 1 , wherein the plurality of gate structures is over one or more semiconductor fins.

6 . An integrated circuit structure, comprising:

a plurality of gate structures, each of the gate structures comprising a metal gate electrode;

a plurality of conductive trench contact structures alternating with the plurality of gate structures;

a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers has an uppermost surface co-planar with an uppermost surface of the metal gate electrodes of the plurality of gate structures and co-planar with an uppermost surface of the plurality of conductive trench contact structures;

a single dielectric layer over and in direct physical contact with the metal gate electrodes of the plurality of gate structures, over and in direct physical contact with the plurality of conductive trench contact structures, and over and in direct physical contact with the plurality of dielectric spacers, the single dielectric layer having a planar uppermost surface;

an opening in the single dielectric layer, the opening exposing one of the plurality of conductive trench contact structures; and

a conductive via in the opening, the conductive via in direct physical contact with the one of the plurality of conductive trench contact structures, and the conductive via having an uppermost surface co-planar with the planar uppermost surface of the single dielectric layer.

7 . The integrated circuit structure of claim 6 , wherein the opening extends into a portion of the one of the plurality of conductive trench contact structures.

8 . The integrated circuit structure of claim 6 , wherein the plurality of gate structures is over one or more stacks of semiconductor nanowires.

9 . The integrated circuit structure of claim 6 , wherein the plurality of gate structures is over one or more stacks of semiconductor nanoribbons.

10 . The integrated circuit structure of claim 6 , wherein the plurality of gate structures is over one or more semiconductor fins.

11 . A computing device, comprising:

a board; and

a component coupled to the board, the component including an integrated circuit structure, comprising:

a plurality of gate structures, each of the gate structures comprising a metal gate electrode;

a plurality of conductive trench contact structures alternating with the plurality of gate structures;

a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers has an uppermost surface co-planar with an uppermost surface of the metal gate electrodes of the plurality of gate structures and co-planar with an uppermost surface of the plurality of conductive trench contact structures;

a single dielectric layer over and in direct physical contact with the metal gate electrodes of the plurality of gate structures, over and in direct physical contact with the plurality of conductive trench contact structures, and over and in direct physical contact with the plurality of dielectric spacers, the single dielectric layer having a planar uppermost surface;

an opening in the single dielectric layer, the opening exposing one of the plurality of gate structures; and

a conductive via in the opening, the conductive via in direct physical contact with the one of the plurality of gate structures, and the conductive via having an uppermost surface co-planar with the planar uppermost surface of the single dielectric layer.

12 . The computing device of claim 11 , further comprising:

a memory coupled to the board.

13 . The computing device of claim 11 , further comprising:

a communication chip coupled to the board.

14 . The computing device of claim 11 , further comprising:

a camera coupled to the board.

15 . The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

16 . A computing device, comprising:

a board; and

a component coupled to the board, the component including an integrated circuit structure, comprising:

a plurality of gate structures, each of the gate structures comprising a metal gate electrode;

a plurality of conductive trench contact structures alternating with the plurality of gate structures;

a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers has an uppermost surface co-planar with an uppermost surface of the metal gate electrodes of the plurality of gate structures and co-planar with an uppermost surface of the plurality of conductive trench contact structures;

a single dielectric layer over and in direct physical contact with the metal gate electrodes of the plurality of gate structures, over and in direct physical contact with the plurality of conductive trench contact structures, and over and in direct physical contact with the plurality of dielectric spacers, the single dielectric layer having a planar uppermost surface;

an opening in the single dielectric layer, the opening exposing one of the plurality of conductive trench contact structures; and

a conductive via in the opening, the conductive via in direct physical contact with the one of the plurality of conductive trench contact structures, and the conductive via having an uppermost surface co-planar with the planar uppermost surface of the single dielectric layer.

17 . The computing device of claim 16 , further comprising:

a memory coupled to the board.

18 . The computing device of claim 16 , further comprising:

a communication chip coupled to the board.

19 . The computing device of claim 16 , further comprising:

a camera coupled to the board.

20 . The computing device of claim 16 , wherein the component is a packaged integrated circuit die.