Memory circuitry and method used in forming memory circuitry
A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The stack in the stair-step region comprises a cavity comprising a flight of stairs in a vertical cross-section along a first direction. The first tiers are conductive and the second tiers are insulative in a finished-circuitry construction. An insulating lining is formed in the cavity atop treads of the stairs and laterally-over sidewalls of the cavity that are along the first direction. Individual of the treads comprise conducting material of one of the conductive tiers in the finished-circuitry construction. The insulating lining is thicker in a bottom part of the cavity than over the sidewalls of the cavity that are above the bottom part. Insulative material is formed in the cavity directly above the insulating lining. Conductive vias are formed through the insulative material and the insulating lining. Individual of the conductive vias are directly above and directly against the conducting material of the tread of individual of the stairs. Other embodiments, including structure, are disclosed.
1 . A method used in forming memory circuitry, comprising:
forming a stack comprising vertically-alternating first tiers and second tiers, the stack extending from a memory-array region into a stair-step region along a first direction, the first tiers being conductive and the second tiers being insulative in a finished-circuitry construction;
forming cavities in the stack in the stair-step region that individually comprise a flight of stairs in a vertical cross-section along the first direction, the cavities being spaced relative one another in the first direction, one of the cavities being vertically-shallower in the stack than another of the cavities that is vertically-deeper in the stack;
forming an insulating lining in the vertically-shallower cavity and in the vertically-deeper cavity atop treads of the stairs and laterally-over sidewalls of the respective cavity that are along the first direction, individual of the treads comprising conducting material of one of the conductive tiers in the finished-circuitry construction, the insulating lining being thicker in a bottom part of the respective cavity than over the sidewalls of the respective cavity that are above the respective bottom part, the insulating lining being thicker in the bottom part of the vertically-shallower cavity than in the bottom part of the vertically-deeper cavity;
forming insulative material in the vertically-shallower cavity and in the vertically-deeper cavity directly above the insulating lining therein; and
forming conductive vias through the insulative material and the insulating lining in the vertically-shallower cavity and in the vertically-deeper cavity, individual of the conductive vias being directly above and directly against the conducting material of the tread of individual of the stairs.
2 . The method of claim 1 wherein the insulating lining at least predominantly comprises silicon nitride.
3 . The method of claim 1 wherein the insulative material and the insulating lining are of different compositions relative one another.
4 . The method of claim 3 wherein the insulating lining at least predominantly comprises silicon nitride and the insulative material at least predominantly comprises silicon dioxide.
5 . The method of claim 1 wherein the insulative material and the insulating lining are of the same composition relative one another.
6 . The method of claim 1 comprising removing all of the insulating lining from being over the sidewalls of the respective cavity that are above the respective bottom part.
7 . The method of claim 6 wherein the removing removes some and only some of the insulating lining that is in the bottom part thereby reducing its thickness in the bottom part.
8 . The method of claim 1 wherein the insulating lining remains over the respective sidewalls above the respective bottom part in the finished circuitry construction.