IP Library Granted Patent US 12707952
Granted Patent B2
US 12707952 · App. 18/220,432 · Granted Aug 11, 2026

Semiconductor device including BSPDN structures in small-CPP area and large-CPP area

Inventors: Panjae Park (Halfmoon, NY); Kang-ill Seo (Springfield, VA)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H10W20/20H10D30/43H10D30/6729H10D30/6735H10D30/6757H10D62/121H10D64/258
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Quick Facts
Patent No.
US 12707952
App. No.
18/220,432
Granted
Aug 11, 2026
Kind
B2
Abstract

Provided is a semiconductor device in which a large-CPP area includes a 1 st source/drain structure; a 1 st frontside contact structure, at a front side of the semiconductor device, connected to the 1 st source/drain structure; a 1 st via structure, at a lateral side of the 1 st source/drain structure, connected to the 1 st frontside contact structure; a 2 nd via structure on the 1 st frontside via structure; a 1 st frontside metal line, at the front side of the semiconductor device, connected to the 2 nd via structure; and a 1 st backside metal line, at a back side of the semiconductor device, connected to the 1 st via structure.

Claims (66)

1 . A semiconductor device comprising:

a 1 st source/drain structure;

a 2 nd source/drain structure;

a 1 st frontside contact structure, at a front side of the semiconductor device, connected to the 1 st source/drain structure;

a 1 st via structure on the 1 st frontside contact structure;

a 2 nd via structure, at a lateral side of the 2 nd source/drain structure;

a 3 rd via structure on the 2 nd via structure;

a 2 nd frontside contact structure, at the front side of the semiconductor device, connected to the 2 nd source/drain structure and the 2 nd via structure;

a 1 st frontside metal line, at the front side of the semiconductor device, connected to the 1 st via structure;

a 1 st backside contact structure, at a back side of the semiconductor device, connected to the 1 st source/drain structure; and

a 1 st backside metal line, at the back side of the semiconductor device, connected to the 1 st backside contact structure.

2 . The semiconductor device of claim 1 , wherein the 1 st backside contact structure is formed in a backside isolation structure.

3 . The semiconductor device of claim 1 , further comprising:

a 2 nd frontside metal line, at the front side of the semiconductor device, connected to the 3 rd via structure; and

a 2 nd backside metal line, at the back side of the semiconductor device, connected to the 2 nd via structure.

4 . The semiconductor device of claim 3 , wherein the 2 nd backside metal line is formed in a backside isolation structure, and

wherein the 2 nd via structure is connected to the 2 nd backside metal line in an inside of the backside isolation structure.

5 . The semiconductor device of claim 3 , wherein the 2 nd via structure has a greater aspect ratio than the 1 st via structure.

6 . The semiconductor device of claim 3 , wherein an aspect ratio of the 2 nd via structure is greater than an aspect ratio of each of the 1 st via structure and the 3 rd via structure.

7 . The semiconductor device of claim 3 , further comprising:

a 4 th via structure;

a 5 th via structure on the 4 th via structure;

a 3 rd frontside metal line, at the front side of the semiconductor device, connected to the 5 th via structure; and

a 3 rd backside metal line, at the back side of the semiconductor device, connected to the 4 th via structure.

8 . The semiconductor device of claim 7 , wherein the 3 rd backside metal line is formed in a substrate or a backside isolation structure, and

wherein the 4 th via structure is connected to the 3 rd backside metal line in an inside of the substrate or the backside isolation structure.

9 . The semiconductor device of claim 7 , wherein an aspect ratio of the 4 th via structure is equal to the aspect ratio of the 2 nd via structure and greater than an aspect ratio of each of the 3 rd via structure and the 5 th via structure.

10 . The semiconductor device of claim 3 , further comprising:

a 1 st gate structure adjacent to the 1 st source/drain structure; and

a 2 nd gate structure adjacent to the 2 nd source/drain structure,

wherein a gate pitch between a plurality of gate structures comprising the 2 nd gate structure is greater than a gate pitch between a plurality of gate structures comprising the 1 st gate structure.

11 . The semiconductor device of claim 3 , further comprising:

a 1 st gate structure adjacent to the 1 st source/drain structure; and

a 2 nd gate structure adjacent to the 2 nd source/drain structure,

wherein the 2 nd gate structure has a greater gate length than the 1 st gate structure in a channel-length direction.

12 . The semiconductor device of claim 3 , further comprising:

a 1 st channel structure connected to the 1 st source/drain structure; and

a 2 nd channel structure connected to the 2 nd source/drain structure,

wherein the 2 nd channel structure has a greater length than the 1 st channel structure.

13 . A semiconductor device comprising:

a 1 st source/drain structure;

a 1 st frontside contact structure, at a front side of the semiconductor device, connected to the 1 st source/drain structure;

a 1 st via structure, at a lateral side of the 1 st source/drain structure, connected to the 1 st frontside contact structure;

a 2 nd via structure on the 1 st via structure;

a 1 st frontside metal line, at the front side of the semiconductor device, connected to the 2 nd via structure; and

a 1 st backside metal line, at a back side of the semiconductor device, connected to the 1 st via structure.

14 . The semiconductor device of claim 13 , wherein the 1 st backside metal line is formed in a substrate or a backside isolation structure.

15 . The semiconductor device of claim 14 , wherein the 2 nd via structure is extended to an inside of the substrate or the backside isolation structure to be connected to the 1 st backside metal line.

16 . The semiconductor device of claim 14 , wherein an aspect ratio of the 1 st via structure is greater than an aspect ratio than the 2 nd via structure.

17 . The semiconductor device of claim 13 , wherein the 1 st source/drain structure is the closest to a boundary of the semiconductor device among a plurality of source/drain structures in the semiconductor device.

18 . The semiconductor device of claim 13 , further comprising:

a 2 nd source/drain structure vertically above the 1 st source/drain structure;

a 2 nd frontside contact structure, at the front side of the semiconductor device, connected to the 2 nd source/drain structure;

a 3 rd via structure on the 2 nd frontside contact structure; and

a 2 nd frontside metal line, at the front side of the semiconductor device, connected to the 3 rd via structure.

19 . A semiconductor device comprising:

a lower source/drain structure;

an upper source/drain structure above the lower source/drain structure;

an upper contact structure on the upper source/drain structure;

a 1 st via structure on the 1 st lower source/drain structure;

a 2 nd via structure on the 1 st via structure;

a frontside metal line, at a front side of the semiconductor device, connected to the 2 nd via structure;

a backside contact structure, at a back side of the semiconductor device, connected to the lower source/drain structure; and

a backside metal line, at the back side of the semiconductor device, connected to the backside contact structure,

wherein the upper contact structure is connected to the 2 nd via structure.

20 . The semiconductor device of claim 19 , wherein the first via structure is at a lateral side of the upper source/drain structure.