IP Library Granted Patent US 12707953
Granted Patent B2
US 12707953 · App. 18/221,696 · Granted Aug 11, 2026

Semiconductor device including self-aligned backside contact structure formed based on contact isolation layer

Inventors: Myung Yang (Niskayuna, NY); Wonhyuk Hong (Clifton Park, NY); Myunghoon Jung (Clifton Park, NY); Jongjin Lee (Clifton Park, NY); Jaejik Baek (Watervliet, NY); Kang-ill Seo (Albany, NY)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H10W20/20H10D30/014H10D30/43H10D30/6735H10D30/6757H10D62/121H10D62/151H10D84/0128H10D84/013H10D84/0149H10D84/0151H10D84/038H10D84/83
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Quick Facts
Patent No.
US 12707953
App. No.
18/221,696
Granted
Aug 11, 2026
Kind
B2
Abstract

A semiconductor device includes: at least one transistor comprising source/drain regions and 1 st gate structure; a contact isolation layer below the 1 st gate structure; and a backside contact plug connected to at least one of the 1 st source/drain regions, wherein the backside contact plug is formed below the 1 st source/drain region and extended to a region below the 1 st gate structure, and isolated from the 1 st gate structure by the contact isolation layer.

Claims (46)

1 . A semiconductor device comprising:

a 1 st transistor comprising 1 st source/drain regions, a 1 st gate structure, and a 1 st channel layer structure;

a contact isolation layer below the 1 st gate structure; and

a backside contact plug connected to a first one of the 1 st source/drain regions,

wherein the backside contact plug is below the first one of the 1 st source/drain regions and extends to a region below the 1 st gate structure, and isolated from the 1 st gate structure by the contact isolation layer,

wherein the contact isolation layer extends below the 1 st channel layer structure, but does not extend below the first one of the 1 st source/drain regions, and

wherein a first sidewall of the contact isolation layer has less curvature than a second sidewall of the contact isolation layer that is opposite the first sidewall.

2 . The semiconductor device of claim 1 , wherein the contact isolation layer comprises silicon nitride.

3 . The semiconductor device of claim 1 , wherein the backside contact plug is isolated from another circuit element by an isolation structure formed below the first one of the 1 st source/drain regions.

4 . The semiconductor device of claim 3 , wherein the contact isolation layer and the isolation structure comprise different materials.

5 . The semiconductor device of claim 4 , wherein the contact isolation layer comprises silicon nitride.

6 . The semiconductor device of claim 1 , further comprising:

a 2 nd transistor comprising 2 nd source/drain regions and a 2 nd gate structure; and

a 1 st isolation structure isolating one of the 2 nd source/drain regions from one of the 1 st source/drain regions,

wherein the 2 nd transistor is adjacent to the 1 st transistor in a 1 st horizontal direction,

wherein a shallow trench isolation (STI) region is formed between the one of the 2 nd source/drain regions and the one of the 1 st source/drain regions and below the 1 st isolation structure, and

wherein the contact isolation layer is formed in the STI region.

7 . The semiconductor device of claim 6 , wherein the contact isolation layer and the 1 st isolation structure comprise different materials.

8 . The semiconductor device of claim 7 , wherein the contact isolation layer comprises silicon nitride, and the 1 st isolation structure comprises silicon oxide.

9 . The semiconductor device of claim 6 , wherein the backside contact plug is formed in a 2 nd isolation structure below the first one of the 1 st source/drain regions, and

wherein the backside contact plug is extended to a region below the STI region.

10 . The semiconductor device of claim 1 , further comprising a 2 nd transistor comprising 2 nd source/drain regions and a 2 nd gate structure, the 2 nd transistor stacked on the 1 st transistor,

wherein one of the 2 nd source/drain regions is formed-above the first one of the 1 st source/drain regions and isolated from the first one of the 1 st source/drain regions through an isolation structure that comprises a material different from a material included in the contact isolation layer.

11 . The semiconductor device of claim 1 , wherein the first sidewall of the contact isolation layer is linear, and the second sidewall of the contact isolation layer that is opposite the first sidewall has a curved shape.

12 . The semiconductor device of claim 1 , wherein the second sidewall has a curved shape that extends into the backside contact plug.

13 . The semiconductor device of claim 1 , wherein the contact isolation layer has a first width that is same as a second width of the 1 st channel layer structure.

14 . A semiconductor device comprising:

a 1 st transistor comprising 1 st source/drain regions, a 1 st gate structure, and a 1 st channel layer structure;

a contact isolation layer below a first one of the 1 st source/drain regions;

a backside contact plug connected to the first one of the 1 st source/drain regions; and

a shallow trench isolation (STI) region at a side of the first one of the 1 st source/drain regions,

wherein the STI region comprises the contact isolation layer,

wherein the backside contact plug is extended to a region below the STI region,

wherein the contact isolation layer extends below the 1 st channel layer structure, but does not extend below the first one of the 1 st source/drain regions, and

wherein a first sidewall of the contact isolation layer has less curvature than a second sidewall of the contact isolation layer that is opposite the first sidewall.

15 . The semiconductor device of claim 14 , further comprising an isolation structure below the first one of the 1 st source/drain regions and at a side of the backside contact plug,

wherein the contact isolation layer is extended to a region below the 1 st gate structure.

16 . The semiconductor device of claim 15 , wherein a bottom surface of the STI region is below a level of a bottom surface of the contact isolation layer below the 1 st gate structure and a level of a bottom surface of the first one of the 1 st source/drain regions.

17 . The semiconductor device of claim 16 , wherein the contact isolation layer has an etch selectivity against the isolation structure, or the contact isolation layer has an etch rate different from that of the isolation structure.

18 . The semiconductor device of claim 15 , wherein the contact isolation layer and the isolation structure comprise different materials.

19 . The semiconductor device of claim 14 , wherein a portion of the backside contact plug contacting the STI region has a different shape as an opposite portion of the backside contact plug.

20 . The semiconductor device of claim 14 , further comprising:

a 2 nd transistor comprising 2 nd source/drain regions and a 2 nd gate structure; and

an isolation structure isolating one of the 2 nd source/drain regions from the first one of the 1 st source/drain regions,

wherein the 2 nd transistor is adjacent to the 1 st transistor in a horizontal direction, and

wherein the contact isolation layer and the isolation structure comprise different materials.