Through-substrate-via cell
A semiconductor structure according to the present disclosure includes a substrate; a through substrate via (TSV) cell over the substrate; and a TSV extending through the TSV cell and the substrate. The TSV cell includes a guard ring structure extending around a perimeter of the TSV cell, and a buffer zone surrounded by the guard ring. The buffer zone includes first dummy transistors, and second dummy transistors. Each of the first dummy transistors includes two first type epitaxial features, a first plurality of nanostructures extending between the two first type epitaxial features, and a first isolation gate structure wrapping over the first plurality of nanostructures. Each of the second dummy transistors includes two second type epitaxial feature, a second plurality of nanostructures extending between the two first type epitaxial features, and a second isolation gate structure wrapping over the second plurality of nanostructures.
1 . A semiconductor structure, comprising:
a substrate;
a through substrate via (TSV) cell disposed over the substrate; and
a TSV extending through the TSV cell and the substrate,
wherein the TSV cell comprises:
a guard ring structure extending continuously around a perimeter of the TSV cell, and
a buffer zone surrounded by the guard ring structure,
wherein the buffer zone comprises:
a plurality of first dummy transistors, and
a plurality of second dummy transistors,
wherein each of the plurality of first dummy transistors comprises:
two first type epitaxial features,
a first plurality of nanostructures extending between the two first type epitaxial features, and
a first isolation gate structure extending through the first plurality of nanostructures,
wherein each of the plurality of second dummy transistors comprises:
two second type epitaxial features,
a second plurality of nanostructures extending between the two first type epitaxial features, and
a second isolation gate structure extending through the second plurality of nanostructures.
2 . The semiconductor structure of claim 1 ,
wherein the two first type epitaxial features comprise silicon (Si) and an n-type dopant,
wherein the two second type epitaxial features comprise silicon germanium (SiGe) and a p-type dopant.
3 . The semiconductor structure of claim 1 ,
wherein the substrate comprises silicon (Si),
wherein the TSV comprises copper (Cu), aluminum (Al), cobalt (Co), copper alloy, tantalum (Ta), titanium (Ti), or tungsten (W).
4 . The semiconductor structure of claim 1 , wherein the first isolation gate structure and the second isolation gate structure comprise silicon nitride.
5 . The semiconductor structure of claim 1 , wherein a portion of the first isolation gate structure extends into the substrate,
wherein a portion of the second isolation gate structure extends into the substrate.
6 . The semiconductor structure of claim 1 , further comprises:
a first void disposed among the first plurality of nanostructures; and
a second void disposed among the second plurality of nanostructures.
7 . The semiconductor structure of claim 1 , wherein, from a top view, the TSV cell comprises a square shape.
8 . The semiconductor structure of claim 1 , wherein, from a top view, the TSV comprises a circular shape.
9 . A semiconductor structure, comprising:
a substrate comprising a first region and a second region;
a plurality of n-type transistors and plurality of p-type transistors in the first region; and
a plurality of first-type dummy transistor and a plurality of second-type dummy transistor in the second region,
wherein each of the plurality of n-type transistors comprises:
two n-type source/drain features,
a first plurality of nanostructures extending between the two n-type source/drain features, and
a first gate structure wrapping around each of the first plurality of nanostructures,
wherein each of the plurality of p-type transistors comprises:
two p-type source/drain features,
a second plurality of nanostructures extending between the two p-type source/drain features, and
a second gate structure wrapping around each of the second plurality of nanostructures,
wherein each of the plurality of first-type dummy transistors comprises:
two n-type epitaxial features,
a third plurality of nanostructures extending between the two n-type epitaxial features, and
a first dielectric gate structure extending through the third plurality of nanostructures,
wherein each of the plurality of second-type dummy transistors comprises:
two p-type epitaxial features,
a fourth plurality of nanostructures extending between the two p-type epitaxial features, and
a second dielectric gate structure extending through the fourth plurality of nanostructures.
10 . The semiconductor structure of claim 9 , wherein the second region further comprises a guard ring structure extending continuously around a perimeter of the second region.
11 . The semiconductor structure of claim 10 , further comprising:
a through via extending through the second region and the substrate.
12 . The semiconductor structure of claim 9 ,
wherein the first gate structure and the second gate structure comprise a metal,
wherein the first dielectric gate structure and the second dielectric gate structure are free of any metal.
13 . The semiconductor structure of claim 9 , wherein the first dielectric gate structure and the second dielectric gate structure comprise silicon nitride.
14 . The semiconductor structure of claim 9 , wherein dimensions of the first plurality of nanostructures are substantial the same as dimensions of the third plurality of nanostructures.
15 . The semiconductor structure of claim 9 ,
wherein the two n-type epitaxial features comprise silicon (Si) and an n-type dopant,
wherein the two p-type epitaxial features comprise silicon germanium (SiGe) and a p-type dopant.
16 . The semiconductor structure of claim 9 ,
wherein a portion of the first dielectric gate structure is disposed among the third plurality of nanostructures,
wherein a portion of the second dielectric gate structure is disposed among the fourth plurality of nanostructures.
17 . The semiconductor structure of claim 16 , further comprises:
a first void disposed among the third plurality of nanostructures; and
a second void disposed among the fourth plurality of nanostructures.
18 . A method, comprising:
receiving an intermediate structure comprising:
a substrate comprising a first region and a second region, and
a stack over the first region and the second region, the stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers;
patterning the stack and a portion of the substrate to form a first fin-shaped structure over the first region and a second fin-shaped structure over the second region;
forming a first dummy gate stack over a channel region of the first fin-shaped structure and a second dummy gate stack over a channel region of the second fin-shaped structure;
etching source/drain regions of the first fin-shaped structure and the second fin-shaped structure to form source/drain recesses;
forming epitaxial features in the source/drain recesses;
selectively removing the plurality of sacrificial layers in the channel regions of the first fin-shaped structure and the second fin-shaped structure to form first channel members over the first region and second channel members over the second region;
selectively forming a gate structure to wrap around each of the first channel members; and
selectively forming a dielectric gate structure to wrap over each of the second channel members.
19 . The method of claim 18 , wherein the dielectric gate structure is free of any metal.
20 . The method of claim 18 , wherein the dielectric gate structure consists essentially of silicon nitride.