Memory device having backside power vias

1 . A semiconductor structure, comprising:

a first source/drain (S/D) epitaxial feature;

a second S/D epitaxial feature adjacent to the first S/D epitaxial feature;

an insulating structure between the first and the second S/D epitaxial features;

a shared S/D contact over top surfaces of the first and the second S/D epitaxial features, wherein a center portion of the shared S/D contact is directly between a side surface of the first S/D epitaxial feature and a side surface of the second S/D epitaxial feature, wherein the center portion is directly above the insulating structure; and

a backside via penetrating through the insulating structure to directly land on a bottom surface of the center portion.

2 . The semiconductor structure of claim 1 , wherein the first and the second S/D epitaxial features are S/D features for pull-down transistors in a static random access memory (SRAM) structure.

3 . The semiconductor structure of claim 1 , wherein the backside via is electrically connected to a power source or to ground.

4 . The semiconductor structure of claim 1 , further comprising:

a frontside via directly landing on a top surface of the shared S/D contact, wherein the frontside via and the backside via are on opposite sides of the shared S/D contact.

5 . The semiconductor structure of claim 1 , further comprising:

fin active regions under the first and the second S/D epitaxial features, the fin active regions extend lengthwise along a first direction, and each of the fin active regions has a fin width along a second direction perpendicular to the first direction,

wherein the backside via has a via length along the second direction, and the via length is greater than fin width.

6 . The semiconductor structure of claim 5 , wherein a ratio of the via length to the fin width is in a range between about 1.5 to about 4.

7 . The semiconductor structure of claim 5 ,

wherein the shared S/D contact extends lengthwise along the second direction, and the shared S/D contact has a S/D contact width along the first direction,

wherein the backside via has a via width along the first direction, and a ratio of the via width to the S/D contact width is about equal to or greater than 1.

8 . The semiconductor structure of claim 5 , further comprising:

a dielectric layer under the fin active regions, wherein the backside via also penetrates through the dielectric layer to land on the bottom surface of the center portion.

9 . The semiconductor structure of claim 1 , further comprising:

a first gate structure over the first S/D epitaxial feature; and

a second gate structure over the second S/D epitaxial feature,

wherein the backside via substantially spans between a gate separation between the first gate structure and the second gate structure along a lengthwise direction of the first and second gate structures.

10 . A semiconductor structure, comprising:

a first source/drain (S/D) epitaxial feature over a first active region;

a second S/D epitaxial feature over a second active region adjacent to the first active region;

an insulating structure between the first and the second S/D epitaxial features;

a shared S/D contact over top surfaces of the first and the second S/D epitaxial features, wherein a center portion of the shared S/D contact is directly between a side surface of the first S/D epitaxial feature and a side surface of the second S/D epitaxial feature, wherein the center portion is directly above the insulating structure; and

a backside via having a first portion penetrating through the insulating structure to directly land on a bottom surface of the center portion, a second portion penetrating through the first active region to directly land on the first S/D epitaxial feature, and a third portion penetrating through the second active region to directly land on the second S/D epitaxial feature.

11 . The semiconductor structure of claim 10 , further comprising:

frontside silicide layers between the first S/D epitaxial feature and the shared S/D contact and between the second S/D epitaxial feature and the shared S/D contact; and

backside silicide layers between the first S/D epitaxial feature and the second portion of the backside via and between the second S/D epitaxial feature and the third portion of the backside via.

12 . The semiconductor structure of claim 10 , wherein the first portion of the backside via has a first width along a first direction, the second portion of the backside via has a second width along the first direction, the third portion of the backside via has a third width along the first direction, and the first width is greater than the second width and greater than the third width.

13 . The semiconductor structure of claim 12 , wherein the backside via further comprises a horizontal fourth portion that connects the first, second, and third portions together, and the first, second, and third portions are laterally distanced from each other.

14 . The semiconductor structure of claim 13 ,

wherein the first and second active regions have a fin width along the first direction,

wherein the first active region is spaced away from the second active region by a fin spacing along the first direction,

wherein the horizontal fourth portion has a backside via length about equal to two times the fin width plus the fin spacing.

15 . The semiconductor structure of claim 10 , wherein the backside via has a sloped surface extending upwards from a top surface of the second portion to a top surface of the first portion.

16 . A semiconductor structure, comprising:

a first source/drain (S/D) epitaxial feature over a first active region;

a second S/D epitaxial feature over a second active region adjacent to the first active region;

an insulating structure between the first and the second S/D epitaxial features;

a shared S/D contact over top surfaces of the first and the second S/D epitaxial features, wherein a center portion of the shared S/D contact is directly between a side surface of the first S/D epitaxial feature and a side surface of the second S/D epitaxial feature, wherein the center portion is directly above the insulating structure; and

a backside slot via landing on bottom surfaces of the shared S/D contact, the first S/D epitaxial feature, and the second S/D epitaxial feature, wherein the backside slot via has a coplanar bottom surface.

17 . The semiconductor structure of claim 16 ,

wherein the backside slot via includes a first portion penetrating through the insulating structure to land on a bottom surface of the center portion, a second portion penetrating through the first active region to land on the first S/D epitaxial feature, and a third portion penetrating through the second active region to land on the second S/D epitaxial feature, wherein the first, second, and third portions are laterally distanced from each other,

wherein the backside slot via further includes a horizontal fourth portion that connects the first, second, and third portions together.

18 . The semiconductor structure of claim 17 , wherein the first portion has a greater width along a first direction than widths of the second and the third portions.

19 . The semiconductor structure of claim 16 , further comprising:

a frontside via landing on a top surface of the shared S/D contact, wherein the frontside via and the backside slot via are on opposite sides of the shared S/D contact.

20 . The semiconductor structure of claim 16 , wherein the first and the second S/D epitaxial features are S/D features for pull-down transistors in a static random access memory (SRAM) structure.