Method of forming a cap layer for sealing an air gap, and semiconductor device

1 . A method of forming a cap layer for sealing an air gap, the method comprising:

forming a line feature, which includes a gate and a gate spacer formed on a sidewall of the gate, over a substrate;

forming a first contact etch stop layer (CESL) on a sidewall of the line feature;

forming a sacrificial layer on a sidewall of the first CESL;

forming a liner layer on a sidewall of the sacrificial layer;

removing the sacrificial layer to form an air gap which is bordered at the first CESL and the liner layer and which is adjacent to the line feature;

in a stage where an etching process is performed, etching back upper ends of the gate spacer, the first CESL and the liner layer to widen an opening of the air gap; and

forming a cap layer to seal the opening of the air gap thus widened,

the substrate including source/drain regions and a fin between the source/drain regions, the line feature being formed on the fin, wherein forming the first CESL includes:

forming a CESL material over the gate, the gate spacer and epitaxy regions;

forming an interlayer dielectric (ILD) layer over the CESL material; and

planarizing the ILD layer where a portion of the CESL material is removed during the planarization to expose the gate and to form the first CESL on a sidewall of the gate spacer and over the epitaxy regions,

the method further comprising:

replacing the gate of the line feature with a gate structure; and

subsequent to replacing the gate of the line feature and prior to forming the sacrificial layer, removing the ILD layer and the first CESL over the epitaxy regions to form contact holes and to expose the epitaxy regions from the contact holes.

2 . The method of claim 1 , wherein etching back upper ends of the first CESL and the liner layer includes performing anisotropic etching on the upper ends in such a manner that corners of the upper ends are rounded off.

3 . The method of claim 1 , wherein forming a first CESL includes forming the first CESL on a sidewall of the gate spacer.

4 . The method of claim 1 , wherein forming a cap layer includes forming a second CESL over the line feature, the first CESL and the liner layer so that the second CESL partially fills the air gap to form the cap layer.

5 . The method of claim 1 , wherein forming a sacrificial layer includes:

forming a sacrificial film over the line feature, the first CESL and the substrate; and

removing portions of the sacrificial film on top surfaces of the line feature, the first CESL and the substrate so that a remaining portion of the sacrificial film on the sidewall of the first CESL forms the sacrificial layer.

6 . The method of claim 1 , wherein forming a liner layer includes:

forming a liner film over the line feature, the first CESL, the sacrificial layer and the substrate; and

removing portions of the liner film on top surfaces of the line feature, the first CESL, the sacrificial layer and the substrate so that a remaining portion of the liner film on the sidewall of the sacrificial layer forms the liner layer.

7 . The method of claim 1 , subsequent to forming a liner layer and prior to removing the sacrificial layer, further comprising forming a metal contact beside the liner layer, the sacrificial layer being between the line feature and the metal contact.

8 . A method of forming a cap layer for sealing an air gap, the method comprising:

forming epitaxy regions on a semiconductor substrate, the semiconductor substrate including a fin between the epitaxy regions, a dummy gate stack over the fin, and gate spacers formed on sidewalls of the dummy gate stack;

forming first contact etch stop layers (CESLs) on sidewalls of the dummy gate structure, wherein forming the first CESLs includes

forming a CESL material over the dummy gate stack, the gate spacers and the epitaxy regions,

forming an interlayer dielectric (ILD) layer over the CESL material, and

planarizing the ILD layer where a portion of the CESL material is removed during the planarization to expose the dummy gate stack and to form the first CESLs on sidewalls of the gate spacers and over the epitaxy regions;

replacing the dummy gate stack with a gate structure;

forming sacrificial layers on sidewalls of the first CESLs;

forming liner layers on sidewalls of the sacrificial layers;

forming contact plugs beside the liner layers and over the epitaxy regions;

removing the sacrificial layers to form air gaps, each of the air gaps being bordered at one of the first CESLs and a corresponding one of the liner layers adjacent to said one of the first CESLs, the contact plugs being spaced apart from the gate structure by the air gaps, respectively;

widening openings of the air gaps by etching back upper ends of the first CESLs and the liner layers;

forming cap layers in upper ends of the air gaps to seal the openings of the air gaps thus widened; and

subsequent to replacing the dummy gate stack and prior to forming the sacrificial layers, removing the ILD layer and the first CESLs over the epitaxy regions to form contact holes and to expose the epitaxy regions from the contact holes.

9 . The method of claim 8 , wherein forming the sacrificial layers includes:

forming a sacrificial film over the gate structure, the gate spacers, the first CESLs and the epitaxy regions; and

removing portions of the sacrificial film on top surfaces of the gate structure, the gate spacers, the first CESLs and the epitaxy regions so as to form the sacrificial layers on the sidewalls of the first CESLs.

10 . The method of claim 8 , wherein forming the liner layers includes:

forming a liner film over the gate structure, the gate spacers, the first CESLs, the sacrificial layers and the epitaxy regions; and

removing portions of the liner film on top surfaces of the gate structure, the gate spacers, the first CESLs, the sacrificial layers and the epitaxy regions so as to form the liner layers on the sidewalls of the sacrificial layers.

11 . The method of claim 8 , wherein forming contact plugs includes:

forming silicide layers respectively on the epitaxy regions exposed from the contact holes;

filling the contact holes with a conductive material; and

planarizing the conductive material to form the contact plugs in the contact holes, respectively.

12 . The method of claim 11 , wherein widening openings of the air gaps includes:

etching back upper ends of the gate spacers when etching back the upper ends of the first CESLs and the liner layers.

13 . The method of claim 11 , wherein widening openings of the air gaps includes:

etching back the upper ends of the first CESLs and the liner layers by using an anisotropic etching process to round off corners of the upper ends.

14 . The method of claim 8 , wherein forming the cap layers includes

forming a second CESL over the gate structure and the contact plugs, the second CESL partially filling the air gaps to form cap layers to seal the openings of the air gaps.

15 . A semiconductor device comprising:

a semiconductor substrate;

a first conductor disposed on the semiconductor substrate;

an air gap structure disposed on the semiconductor substrate and adjacent to the first conductor, the air gap structure having an air gap;

a second conductor disposed adjacent to the first conductor and spaced apart from the first conductor by the air gap structure;

a cap layer disposed at an upper end of the air gap structure and sealing an opening of the air gap, the cap layer having a top portion and a bottom portion, a dimension of the top portion being greater than that of the bottom portion; and

an epitaxy region disposed in a recess of the semiconductor substrate,

wherein the semiconductor substrate includes a fin beside the epitaxy region, the first conductor is a gate structure that is disposed on the fin, and the second conductor is a contact plug that is disposed over the epitaxy region; and

wherein the air gap structure includes a contact etch stop layer (CESL) disposed on a sidewall of the gate structure and a liner layer disposed on a sidewall of the contact plug, the CESL and the liner layer bordering the air gap therebetween, upper ends of the CESL and the liner spacer being in direct contact with the cap layer, and having corners rounded off to accommodate the cap layer;

the semiconductor device further comprising a gate spacer disposed on a sidewall of the gate structure, wherein an upper end of the gate spacer also has a corner rounded off to form a receiving surface for accommodating the top portion of the cap layer, the receiving surface being inclined toward the semiconductor substrate from one side adjacent to the gate structure to an opposite side adjacent to the air gap.

16 . The semiconductor device of claim 15 , wherein the CESL is disposed on a sidewall of the gate spacer.

17 . The semiconductor device of claim 15 , further comprising another CESL that is disposed over the gate structure and the contact plug, and that partially fills the air gap so as to form the cap layer.

18 . The semiconductor device of claim 17 , further comprising an interlayer dielectric (ILD) layer that is disposed on the another CESL, and a gate via that extends through the ILD layer and the another CESL and that is electrically connected to the gate structure.

19 . The semiconductor device of claim 17 , further comprising a self-aligned contact (SAC) layer disposed between the gate structure and the another CESL, wherein a ratio between a height of the cap layer and a height of the SAC layer ranges from 15% to 100%.

20 . The semiconductor device of claim 15 , wherein the cap layer has a height ranging from 3 nanometers to 60 nanometers.