Semiconductor devices including backside capacitors and methods of manufacture
Semiconductor devices including backside capacitors and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including a front-side conductive line; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a backside conductive line, the backside conductive line having a line width greater than a line width of the front-side conductive line; and a first capacitor structure coupled to the backside interconnect structure.
1 . A semiconductor device comprising:
a first transistor structure comprising a gate structure surrounding a first nanostructure in a first cross-sectional view, a portion of the gate structure being disposed between the first nanostructure and a second nanostructure in a second cross-sectional view that is perpendicular to the first cross-sectional view, and a source/drain region adjoining the first nanostructure and the second nanostructure;
a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure comprising a front-side conductive line;
a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure comprising a backside conductive line, the backside conductive line having a line width greater than a line width of the front-side conductive line; and
a first capacitor structure coupled to the backside interconnect structure, wherein the first capacitor structure is disposed on the backside of the first transistor structure, and wherein the backside of the first transistor structure and the portion of the gate structure of the first transistor structure are on opposing sides of the second nanostructure of the first transistor structure.
2 . The semiconductor device of claim 1 , wherein the first capacitor structure is coupled to the backside interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.
3 . The semiconductor device of claim 1 , wherein a first conductive contact of the backside interconnect structure is physically and electrically coupled to a second conductive contact of the first capacitor structure, wherein the first conductive contact has a first width, and wherein the second conductive contact has a second width greater than the first width.
4 . The semiconductor device of claim 1 , wherein the first capacitor structure comprises a substrate and a capacitor over the substrate, wherein the second nanostructure is disposed between the gate structure and the substrate.
5 . The semiconductor device of claim 4 , wherein the capacitor extends below a top surface of the substrate.
6 . The semiconductor device of claim 4 , wherein the capacitor further comprises:
a dielectric layer over the substrate and the capacitor; and
a first conductive contact physically and electrically coupled to the capacitor, the first conductive contact extending below a top surface of the substrate.
7 . The semiconductor device of claim 6 , wherein the capacitor further comprises a second conductive contact physically and electrically coupled to the capacitor, the second conductive contact extending below the top surface of the substrate.
8 . A device comprising:
a gate structure along at least three sides of a semiconductor channel region in a first cross-sectional view;
a first source/drain region adjacent the gate structure and the semiconductor channel region in a second cross-sectional view that is perpendicular to the first cross-sectional view;
a gate contact coupled to a surface of the gate structure, the gate contact extending from the surface of the gate structure along a first direction away from the semiconductor channel region;
a first source/drain contact coupled to a surface of the first source/drain region, the first source/drain contact extending from the surface of the first source/drain region along a second direction away from the semiconductor channel region, the second direction being opposite the first direction;
a first interconnect structure coupled to the first source/drain contact opposite the first source/drain region in the second direction; and
a capacitor structure coupled to the first interconnect structure opposite the first source/drain contact in the second direction, wherein the capacitor structure is coupled to the first interconnect structure by dielectric-to-dielectric bonds and metal-to-metal bonds.
9 . The device of claim 8 , further comprising:
a second interconnect structure coupled to the gate contact opposite the gate structure in the first direction; and
an external connector coupled to the second interconnect structure, wherein the capacitor structure comprises a capacitor over a substrate, the substrate being opposite the capacitor in the second direction.
10 . The device of claim 8 , wherein the capacitor structure comprises a capacitor extending along a planar surface of a substrate.
11 . The device of claim 8 , wherein the capacitor structure comprises:
a substrate comprising a first recess;
a capacitor extending along a top surface of the substrate and into the first recess; and
a dielectric layer over the substrate and filling the first recess.
12 . The device of claim 11 , wherein the capacitor structure comprises a first contact extending through the dielectric layer into the first recess to the capacitor.
13 . The device of claim 8 , wherein the capacitor structure comprises:
a substrate comprising a first recess;
a capacitor extending along a surface of the first recess, wherein a top surface of the substrate is free from the capacitor; and
a dielectric layer over the substrate and filling the first recess.
14 . The device of claim 8 , wherein a first contact of the first interconnect structure is coupled to a second contact of the capacitor structure by the metal-to-metal bonds, wherein the first contact has a first width, wherein the second contact has a second width, and wherein a ratio of the second width to the first width is from 3 to 5.
15 . A device comprising:
a device layer comprising a transistor, wherein the transistor comprises:
a stack of nanostructures;
a gate structure surrounding the stack of nanostructures in a first cross-sectional view; and
a source/drain region adjoining the stack of nanostructures in a second cross-sectional view that is perpendicular to the first cross-sectional view;
a front-side interconnect structure on a front-side of the device layer, wherein the front-side interconnect structure includes a front-side source/drain contact electrically coupled to the source/drain region of the transistor, wherein the front-side source/drain contact extends along the gate structure of the transistor;
a backside interconnect structure on a backside of the device layer, the backside interconnect structure comprising:
a backside conductive line that is electrically coupled to the source/drain region of the transistor by a backside source/drain contact, wherein the front-side source/drain contact and the backside source/drain contact are on opposing sides of the source/drain region;
a first insulating layer; and
a first bond pad in the first insulating layer;
a first capacitor structure bonded to the backside interconnect structure, the first capacitor structure comprising:
a capacitor;
a second insulating layer contacting the first insulating layer; and
a second bond pad contacting the first bond pad.
16 . The device of claim 15 , wherein the second bond pad is wider than the first bond pad in a cross-sectional view.
17 . The device of claim 15 , wherein the second bond pad contacts the first insulating layer.
18 . The device of claim 15 , wherein the first capacitor structure further comprises a substrate, wherein the capacitor extends at least partially into the substrate.
19 . The device of claim 18 , wherein the capacitor further extends along a lateral surface of the substrate.
20 . The device of claim 15 , wherein the second bond pad extends continuously from the first insulating layer to an electrode of the capacitor, wherein the second bond pad continuously decreases in width from the first insulating layer to the electrode of the capacitor in a cross-sectional view.