Semiconductor device structure having a multi-layer conductive feature and method making the same

1 . A semiconductor device structure, comprising:

a field-effect transistor formed on a semiconductor substrate, wherein the field-effect transistor includes a gate stack disposed on an active region of the semiconductor substrate, and source/drain (S/D) features formed on the active region and interposed by the gate stack; and

a metal layer in a multilayer dielectric layer, wherein the metal layer and the multilayer dielectric layer belong to a single level of an interconnect structure, wherein the metal layer includes a conductive feature in the multilayer dielectric layer, wherein the conductive feature has a height equal to a first thickness of the multilayer dielectric layer, wherein the conductive feature is electrically connected to one of the S/D features, wherein the conductive feature includes:

a bottom metal feature formed by a single bottom metal layer of a first metal, wherein the bottom metal feature abuts an etch stop layer and an interlayer dielectric layer of the multilayer dielectric layer, wherein the etch stop layer has a second thickness, the interlayer dielectric layer has a third thickness, the second thickness and the third thickness are each less than the first thickness, the single bottom metal layer has a fourth thickness that is greater than the second thickness, the etch stop layer forms a bottom of the multilayer dielectric layer, and the height, the first thickness, the second thickness, the third thickness, and the fourth thickness are along a same direction,

a top metal feature formed by a barrier layer and a top metal layer of a second metal, wherein the second metal is different from the first metal, wherein the top metal feature is over the bottom metal feature, and

wherein the barrier layer wraps the top metal layer and separates the single bottom metal layer from the top metal layer, the barrier layer abuts the interlayer dielectric layer of the multilayer dielectric layer, the barrier layer includes a bottom surface that spans an entire width of the conductive feature, the single bottom metal layer includes a top surface that spans the entire width of the conductive feature, and the bottom surface of the barrier layer abuts the top surface of the single bottom metal layer.

2 . The semiconductor device structure of claim 1 , wherein the barrier layer and the bottom metal layer combine to form sidewalls of the conductive feature.

3 . The semiconductor device structure of claim 1 , wherein the top metal feature formed by the barrier layer and the top metal layer has a fifth thickness, a sum of the fourth thickness and the fifth thickness is equal to the height, and the fifth thickness is along the same direction as the fourth thickness.

4 . The semiconductor device structure of claim 3 , wherein the fourth thickness is less than the fifth thickness.

5 . The semiconductor device structure of claim 3 , wherein a ratio of the fifth thickness to the fourth thickness ranges between 5 and 1.2.

6 . The semiconductor device structure of claim 1 , wherein the barrier layer and the top metal layer form a top surface of the top metal feature, and the barrier layer forms a bottom surface of the top metal feature.

7 . The semiconductor device structure of claim 3 , wherein:

the fourth thickness ranges between 1 nm and 30 nm;

the fifth thickness ranges between 5 nm and 30 nm; and

the conductive feature has a width ranging between 5 nm and 150 nm.

8 . An interconnect structure, comprising:

a source/drain contact disposed on a source/drain;

a metal via disposed on the source/drain contact, wherein the metal via is disposed in a first plurality of dielectric layers of a via level of an interconnect structure, wherein the first plurality of dielectric layers has a first thickness along a first direction, the metal via has a first height along the first direction between a top of the metal via and a bottom of the metal via, and the first height is equal to the first thickness; and

a metal line disposed on the metal via, wherein the metal line is disposed in a second plurality of dielectric layers of a metal line level of the interconnect structure, the second plurality of dielectric layers has a second thickness along the first direction, the source/drain contact, the metal via, and the metal line are sequentially stacked along the first direction, the metal line has a second height along the first direction between a top of the metal line and a bottom of the metal line, the second height is equal to the second thickness, the metal line has a first sidewall and a second sidewall that extend from the top of the metal line to the bottom of the metal line, the metal line has a width along a second direction between the first sidewall and the second sidewall, the second direction is different than the first direction, and the metal line includes:

a first metal layer, a second metal layer, and a third metal layer, wherein the first metal layer forms a lower portion of the metal line having a third thickness along the first direction, the second metal layer and the third metal layer combine to form an upper portion of the metal line having a fourth thickness along the first direction, a sum of the third thickness and the fourth thickness is equal to the second height of the metal line, and the third thickness is greater than a fifth thickness of a bottom dielectric layer of the second plurality of dielectric layers, wherein the fifth thickness of the bottom dielectric layer of the second plurality of dielectric layers is less than the second thickness of the second plurality of dielectric layers,

wherein the first metal layer extends the width of the metal line and forms a lower portion of the first sidewall of the metal line and a lower portion of the second sidewall of the metal line,

the second metal layer extends the width of the metal line and forms an upper portion of the first sidewall of the metal line and an upper portion of the second sidewall of the metal line,

wherein the first metal layer is between the metal via and the second metal layer and the first metal layer extends from a first sidewall of the second plurality of dielectric layers to a second sidewall of the second plurality of dielectric layers, and

wherein the second metal layer is between the third metal layer and the first metal layer, the second metal layer is between the third metal layer and the second plurality of dielectric layers, and the second metal layer also extends from the first sidewall of the second plurality of dielectric layers to the second sidewall of the second plurality of dielectric layers.

9 . The interconnect structure of claim 8 , wherein the third metal layer has a width that is less than the width of the metal line.

10 . The interconnect structure of claim 8 , wherein the metal via, the first metal layer, and the third metal layer include a same metal material.

11 . The interconnect structure of claim 8 , wherein the metal via, the first metal layer, and the third metal layer include different metal materials.

12 . The interconnect structure of claim 8 , wherein the metal via and the first metal layer include a first metal material and the third metal layer include a second metal material.

13 . The interconnect structure of claim 8 , wherein the metal via includes a first metal material and the first metal layer and the third metal layer include a second metal material.

14 . The interconnect structure of claim 8 , wherein:

the first metal layer is a ruthenium layer;

the second metal layer is a tantalum nitride layer; and

the third metal layer is a copper layer.

15 . The interconnect structure of claim 14 , wherein the metal via is a tungsten layer.

16 . A device structure comprising:

a first etch stop layer having a first thickness, a first interlayer dielectric layer having a second thickness disposed on the first etch stop layer, a second etch stop layer having a third thickness disposed on the first interlayer dielectric layer, and a second interlayer dielectric layer having a fourth thickness disposed on the second etch stop layer, wherein the first etch stop layer, the first interlayer dielectric layer, the second etch stop layer, and the second interlayer dielectric layer are sequentially disposed over a substrate;

a first interconnect structure that extends through the first interlayer dielectric layer and the first etch stop layer and is electrically connected to a conductive feature of a transistor, wherein the first interconnect structure has a fifth thickness that is the same as a sum of the first thickness of the first etch stop layer and the second thickness of the first interlayer dielectric layer, wherein the first thickness is less than the second thickness; and

a second interconnect structure that extends through the second interlayer dielectric layer and the second etch stop layer to the first interconnect structure, wherein the second interconnect structure has a sixth thickness that is the same as a sum of the third thickness of the second etch stop layer and the fourth thickness of the second interlayer dielectric layer, wherein the third thickness is less than the fourth thickness, and wherein the second interconnect structure includes:

a bottom layer having a seventh thickness disposed on the first interconnect structure, wherein sidewalls of the bottom layer interface with the second etch stop layer and the second interlayer dielectric layer, and

a top portion having an eighth thickness disposed on the bottom layer, wherein the eighth thickness is greater than the seventh thickness, a sum of the seventh thickness and the eighth thickness is equal to the sixth thickness, and:

the top portion includes a first top layer and a second top layer over the first top layer;

a bottom of the first top layer interfaces with the bottom layer, sidewalls of the first top layer interface with the second interlayer dielectric layer, and a top of the first top layer interfaces with the second top layer; and

the first top layer separates the second top layer from the bottom layer and the second interlayer dielectric layer.

17 . The device structure of claim 16 , wherein an interface between the first top layer and the bottom layer extends an entire width of the second interconnect structure.

18 . The device structure of claim 17 , wherein a length of an interface between the bottom layer and the first interconnect structure is less than a length of the interface between the first top layer and the bottom layer.

19 . The device structure of claim 16 , wherein:

the first etch stop layer and the second etch stop layer include nitrogen; and

the first interlayer dielectric layer and the second interlayer dielectric layer include silicon and oxygen.

20 . The device structure of claim 16 , wherein:

the first interlayer dielectric layer and the second interlayer dielectric layer have different compositions; and

the first etch stop layer and the second etch stop layer have different compositions.