Semiconductor device assemblies including monolithic silicon structures for thermal dissipation and methods of making the same

1 . A semiconductor device assembly, comprising:

a first semiconductor device including a plurality of electrical contacts on an upper surface thereof;

a monolithic silicon structure having a lower surface in contact with the upper surface of the first semiconductor device, the monolithic silicon structure including a cavity extending from the lower surface into a body of the monolithic silicon structure; and

a second semiconductor device disposed in the cavity and including a plurality of interconnects, each operatively coupled to a corresponding one of the plurality of electrical contacts,

wherein the upper surface of the first semiconductor device includes a region corresponding in shape and size to the lower surface of the monolithic silicon structure, the region completely covered by (i) a first dielectric material and (ii) thermal contacts extending through the first dielectric material,

wherein the lower surface of the monolithic silicon structure and a lower surface of the second semiconductor device are covered by a continuous layer of a second dielectric material and wherein the monolithic silicon structure includes thermal pads extending through the continuous layer of the second dielectric material, and

wherein the lower surface of the monolithic silicon structure and the lower surface of the second semiconductor device are bonded to the upper surface of the first semiconductor device by a hybrid bond interface that includes (i) a dielectric bond between the second dielectric material and the first dielectric material, (ii) metal-metal bonds between corresponding ones of the thermal contacts and the thermal pads, and (iii) metal-metal bonds between corresponding ones of the plurality of interconnects and the plurality of electrical contacts.

2 . The semiconductor device assembly of claim 1 , wherein the monolithic silicon structure has a plan area corresponding in size and shape to a plan area of the first semiconductor device.

3 . The semiconductor device assembly of claim 1 , wherein the plurality of interconnects is a first plurality of interconnects, the cavity is a first cavity, the monolithic silicon structure includes a second cavity extending from the lower surface into the body of the monolithic silicon structure, and further comprising a third semiconductor device disposed in the second cavity and including a second plurality of interconnects, each operatively coupled to a corresponding one of the plurality of electrical contacts.

4 . The semiconductor device assembly of claim 1 , wherein the second semiconductor device includes a vertical stack of electrically coupled memory devices.

5 . The semiconductor device assembly of claim 1 , wherein one or more of the upper surface of the first semiconductor device and the lower surface of the monolithic silicon structure include a redistribution layer.

6 . A semiconductor device assembly, comprising:

a first semiconductor device including an upper surface;

a monolithic silicon structure having a lower surface in contact with the upper surface of the first semiconductor device, the monolithic silicon structure including a cavity extending from the lower surface into a body of the monolithic silicon structure; and

a second semiconductor device directly coupled to the first semiconductor device and disposed in the cavity such that a back surface and a plurality of sidewalls of the second semiconductor device are completely enclosed within the cavity,

wherein the upper surface of the first semiconductor device includes a region corresponding in shape and size to the lower surface of the monolithic silicon structure, the region completely covered by a first dielectric material,

wherein the lower surface of the monolithic silicon structure and a lower surface of the second semiconductor device are covered by a continuous layer of a second dielectric material, and

wherein the lower surface of the monolithic silicon structure and the lower surface of the second semiconductor device are bonded to the upper surface of the first semiconductor device by an oxide-oxide bond between the second dielectric material and the first dielectric material.

7 . The semiconductor device assembly of claim 6 , wherein the cavity is sized such that a gap separates each of the plurality of sidewalls from an interior surface of the cavity.

8 . The semiconductor device assembly of claim 6 , wherein a back surface of the second semiconductor device is adhered to an interior surface of the cavity.

9 . The semiconductor device assembly of claim 6 , wherein the lower surface of the second semiconductor device is coplanar with the lower surface of the monolithic silicon structure.

10 . The semiconductor device assembly of claim 6 , wherein the monolithic silicon structure includes a plurality of outer surfaces coplanar with outer surfaces of the first semiconductor device.

11 . A semiconductor device assembly, comprising:

a first semiconductor device including an upper surface;

a second semiconductor device directly carried by an upper surface of the first semiconductor device; and

a monolithic silicon structure having a lower surface in contact with the upper surface of the first semiconductor device, the monolithic silicon structure including a cavity extending from the lower surface into a body of the monolithic silicon structure and surrounding the second semiconductor device,

wherein the upper surface of the first semiconductor device includes a region corresponding in shape and size to the lower surface of the monolithic silicon structure, the region completely covered by a first dielectric material,

wherein the lower surface of the monolithic silicon structure and a lower surface of the second semiconductor device are covered by a continuous layer of a second dielectric material, and

wherein the lower surface of the monolithic silicon structure and the lower surface of the second semiconductor device are bonded to the upper surface of the first semiconductor device by an oxide-oxide bond between the second dielectric material and the first dielectric material.

12 . The semiconductor device assembly of claim 11 , wherein the monolithic silicon structure has a plan area corresponding in size and shape to a plan area of the first semiconductor device.

13 . The semiconductor device assembly of claim 11 , wherein the lower surface of the second semiconductor device is coplanar with the lower surface of the monolithic silicon structure.

14 . The semiconductor device assembly of claim 11 , wherein the cavity is sized such that a gap separates each of a plurality of sidewalls of the second semiconductor device from an interior surface of the cavity.