IP Library Granted Patent US 12,707,968
Granted Patent B2
US 12,707,968 · App. 19/308,968 · Granted Aug 11, 2026

Heat removing layer surrounding a transistor

Inventors: Chao-Chun Lu (Hsinchu, TW); Wen-Hsien Tu (Hsinchu, TW); Feng-Wu Chen (Hsinchu, TW)
Assignee: INVENTION AND COLLABORATION LABORATORY INC.
H10W40/253H10D30/601H10D30/62H10D62/115H10D64/021H10D84/0147H10D84/0184H10W40/259H10B12/05H10B12/30H10B12/50H10D30/503H10D30/6211H10D30/6212H10D30/63H10D84/85
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,707,968
App. No.
19/308,968
Granted
Aug 11, 2026
Kind
B2
Abstract

A semiconductor circuit structure includes a semiconductor substrate with an original semiconductor surface, an active region within the semiconductor substrate, and a transistor formed based on the active region. The transistor includes a gate structure, a first spacer neighboring to a first sidewall of the gate structure, and a second spacer neighboring to a second sidewall of the gate structure. Wherein a thermal conductivity of the first spacer or the second spacer includes is higher than the thermal conductivity of silicon nitride (Si 3 N 4 ).

Claims (45)

1 . A semiconductor circuit structure comprising:

a semiconductor substrate with an original semiconductor surface;

an active region within the semiconductor substrate; and

a transistor formed within the active region, the transistor comprising:

a gate structure with a gate conductive layer;

a first spacer neighboring to a first sidewall of the gate structure; and

a second spacer neighboring to a second sidewall of the gate structure; and

a shallow trench isolation (STI) region comprising a heat removing layer surrounding the transistor; wherein a top surface of the heat removing layer is higher than that of the gate conductive layer, and a thermal conductivity of the heat removing layer is higher than that of SiO 2 .

2 . The semiconductor circuit structure according to claim 1 , wherein the transistor is a fin field-effect transistor (FinFET), a gate-all-around (GAA) transistor, a recessed gate (RG) transistor or a complementary field-effect transistor (CFET).

3 . The semiconductor circuit structure according to claim 1 , wherein the heat removing layer is within the STI region and isolated from the semiconductor substrate.

4 . The semiconductor circuit structure according to claim 3 , wherein:

a dielectric isolation layer is over the heat removing layer.

5 . The semiconductor circuit structure according to claim 1 , wherein the heat removing layer is located close to the source region or the drain region.

6 . The semiconductor circuit structure according to claim 1 , wherein the heat removing layer is made of a material selected from a group consisting of SiC, h-BN, AlN and the arbitrary combinations thereof.

7 . A semiconductor circuit structure comprising:

a semiconductor substrate with an original semiconductor surface;

an active region within the semiconductor substrate; and

a transistor formed within the active region, the transistor comprising:

a gate structure with a gate conductive layer;

a first spacer neighboring to a first sidewall of the gate structure; and

a second spacer neighboring to a second sidewall of the gate structure;

a channel region covered by the gate structure;

a source structure coupled to a first terminal of the channel region; and

a drain structure coupled to a second terminal of the channel region; wherein the first spacer is between the gate structure and the source structure, and the second spacer is between the gate structure and the drain structure; and

a heat removing layer surrounding the transistor; wherein a top surface of the heat removing layer is higher than that of the gate conductive layer, and a thermal conductivity of the heat removing layer is higher than that of SiO 2 .

8 . The semiconductor circuit structure according to claim 7 , wherein the source structure comprises a first lightly doped drain (LDD) region and a first heavily doped region, and the first spacer covers the first LDD region or the first heavily doped region of the source structure.

9 . The semiconductor circuit structure according to claim 8 , wherein the drain structure comprises a second LDD region and a second heavily doped region, and the second spacer covers the second LDD region or the second heavily doped region of the drain structure.

10 . A semiconductor circuit structure comprising:

a semiconductor substrate with an original semiconductor surface;

an active region within the semiconductor substrate; and

a transistor formed within the active region, the transistor comprising:

a gate structure with a gate conductive layer;

a first spacer neighboring to a first sidewall of the gate structure; and

a second spacer neighboring to a second sidewall of the gate structure; and

a heat removing layer surrounding the transistor; wherein a top surface of the heat removing layer is higher than that of the gate conductive layer, and a thermal conductivity of the heat removing layer is higher than that of SiO 2 ;

wherein the heat removing layer is undoped polysilicon or large-grain silicon.

11 . A semiconductor circuit structure comprising:

a semiconductor substrate with an original semiconductor surface;

an active region within the semiconductor substrate; and

a transistor formed within the active region, the transistor comprising:

a gate structure with a gate conductive layer;

a first spacer neighboring to a first sidewall of the gate structure; and

a second spacer neighboring to a second sidewall of the gate structure;

a heat removing layer surrounding the transistor; wherein a top surface of the heat removing layer is higher than that of the gate conductive layer, and a thermal conductivity of the heat removing layer is higher than that of SiO 2 ; and

a dielectric lying layer covering sidewalls of the heat removing layer to electrically isolated the heat removing layer from the semiconductor substrate.