Heterogeneously integrated liquid electrolyte powered processor
A processing unit includes a substrate, an electrical load, and a microfluidic volume. The electrical load is supported by the first surface of the substrate, and the microfluidic volume is positioned in the second surface of the substrate. The processing unit includes a first electrode positioned in the microfluidic volume and a second electrode positioned in the microfluidic volume. A first TSV connects the first electrode to the electrical load, and a second TSV connects the second electrode to the electrical load. An electrochemical fluid is positioned in the microfluidic volume to provide electrical power to the electrical load and receive heat from the electrical load.
1 . A processing unit comprising:
a processor including:
a substrate having a first surface and an opposite second surface, the substrate being an inactive silicon of the processing unit, and
an electrical load supported by the first surface of the substrate, the electrical load being the active silicon of the processing unit;
an electrochemical generator including:
a microfluidic volume positioned recessed within the second surface of the substrate,
a first electrode positioned in the microfluidic volume;
a second electrode positioned in the microfluidic volume;
a first through silicon via (TSV) through the substrate connecting the first electrode to the electrical load;
a second TSV through the substrate connecting the second electrode to the electrical load; and
an electrochemical fluid positioned in the microfluidic volume to provide electrical power to the electrical load and receive heat from the electrical load.
2 . The processing unit of claim 1 , wherein the electrochemical fluid is a first electrochemical fluid, and a second electrochemical fluid is positioned in the microfluidic volume.
3 . The processing unit of claim 2 , further comprising an ion-transfer membrane between the first electrochemical fluid and the second electrochemical fluid.
4 . The processing unit of claim 2 , wherein the first electrochemical fluid is an anolyte and the second electrochemical fluid is a catholyte.
5 . The processing unit of claim 2 , wherein the first electrochemical fluid and second electrochemical fluid are configured in countercurrent flow.
6 . The processing unit of claim 1 , wherein microfluidic volume has a chamber width less than 500 micrometers.
7 . The processing unit of claim 1 , wherein the electrochemical fluid is a first electrochemical fluid,
the microfluidic volume includes a first portion containing the first electrochemical fluid and a second portion containing a second electrochemical fluid, and
a first portion width is different from a second portion width.
8 . The processing unit of claim 1 , wherein a cross-sectional area of the microfluidic volume changes in a direction of flow of the electrochemical fluid.
9 . The processing unit of claim 1 , wherein a cross-sectional shape of the microfluidic volume changes in a direction of flow of the electrochemical fluid.
10 . The processing unit of claim 1 , wherein the inactive silicon is a silicon wafer.
11 . The processing unit of claim 1 , wherein the first electrode and second electrode are a first set of electrodes positioned in the microfluidic volume, and further comprising a second set of electrodes positioned in the microfluidic volume.
12 . The processing unit of claim 1 , wherein the microfluidic volume includes a first electrochemical chamber and a second electrochemical chamber, and the first electrode and second electrode are a first set of electrodes positioned in the first electrochemical chamber, and a second set of electrodes is positioned in the second electrochemical chamber.
13 . The processing unit of claim 12 , wherein the first electrochemical chamber and the second electrochemical chamber are parallel to one another.
14 . The processing unit of claim 12 , wherein the first electrochemical chamber and the second electrochemical chamber are branches of the microfluidic volume.
15 . A processing unit comprising:
a processor including:
a inactive silicon having a first surface and an opposite second surface;
an active silicon supported by a first surface of the inactive silicon; and
an electrochemical chamber positioned in the inactive silicon, wherein the electrochemical chamber includes:
an ion-transfer membrane dividing the electrochemical chamber include a first portion and a second portion,
a first electrode positioned in a first portion of the electrochemical chamber,
a second electrode positioned in a second portion of the electrochemical chamber,
a pin fin positioned in the electrochemical chamber and configured to support the ion-transfer membrane relative to the inactive silicon,
at least one electrode supported by the pin fin in the electrochemical chamber,
a through silicon via (TSV) in the pin fin and connecting the at least one electrode to the active silicon,
a first electrochemical fluid positioned in the first portion, and
a second electrochemical fluid positioned in the second portion.
16 . The processing unit of claim 15 , wherein the ion-transfer membrane has a plane parallel to the second surface of the substrate.
17 . The processing unit of claim 16 , wherein the first portion, ion-transfer membrane, and second portion are layered in a direction perpendicular to the second surface.
18 . A system for electrochemical generation comprising:
a processing unit including:
a processor including:
inactive silicon having a first surface and an opposite second surface, and
active silicon supported by a first surface of the inactive silicon, and
an electrochemical chamber positioned in the inactive silicon, wherein the electrochemical chamber includes:
an ion-transfer membrane dividing the electrochemical chamber into a first portion and a second portion,
a first electrode positioned in a first portion of the electrochemical chamber,
a second electrode positioned in a second portion of the electrochemical chamber,
a through silicon via (TSV) through at least a portion of the inactive silicon and connecting the first electrode to the active silicon,
a first electrochemical fluid positioned in the first portion, and
a second electrochemical fluid positioned in the second portion;
a first electrochemical fluid storage tank in fluid communication with the first portion;
a second electrochemical fluid storage tank in fluid communication with the second portion; and
a heat exchanger in fluid communication with at least one of the first electrochemical fluid and second electrochemical fluid and configured to exhaust heat from the at least one of the first electrochemical fluid and second electrochemical fluid.
19 . The system of claim 18 , wherein the heat exchanger is a first heat exchanger in fluid communication with the first electrochemical fluid and configured to exhaust heat from the first electrochemical fluid, and
further comprising a second heat exchanger in fluid communication with the second electrochemical fluid and configured to exhaust heat from the second electrochemical fluid.
20 . The system of claim 18 , wherein the processing unit is a first processing unit, and the system further comprises a second processing unit including:
an inactive silicon having a first surface and an opposite second surface,
an active silicon supported by a first surface of the inactive silicon, and
an electrochemical chamber positioned in the substrate, wherein the electrochemical chamber includes:
an ion-transfer membrane dividing the electrochemical chamber include a first portion and a second portion,
a first electrode positioned in a first portion of the electrochemical chamber,
a second electrode positioned in a second portion of the electrochemical chamber,
a through silicon via (TSV) through at least a portion of the substrate and connecting the first electrode to the electrical load,
a first electrochemical fluid positioned in the first portion, and
a second electrochemical fluid positioned in the second portion,
wherein at least the first electrochemical fluid is configured to flow from an outlet of the inactive silicon of the first processing unit to the heat exchanger, and from the heat exchanger to an inlet of the inactive silicon of the second processing unit.