Wafer level multi-die structure formation
An array of dies is formed over a substrate. Each of the dies contains a plurality of functional transistors. A plurality of first seal rings each surround a respective one of the dies in a top view. The first seal rings define a plurality of corner regions that are disposed outside of the first seal rings and between corners of respective subsets of the dies. A plurality of structures is disposed within the corner regions. The structures include test structures, dummy structures, process monitor patterns, alignment marks, or overlay marks. Electrical interconnection elements are disposed between each pair of adjacent dies in the array of dies in the top view. The electrical interconnection elements electrically interconnect the dies in the array with one another. A second seal ring surrounds the array of dies, the first seal rings, and the structures in the top view.
1 . A device, comprising:
an array of dies formed over a substrate, wherein at least some of the dies in the array contains a plurality of functional transistors;
a plurality of first seal rings that surround respective ones of the dies in a top view, wherein the plurality of first seal rings define a plurality of corner regions that are disposed outside of the first seal rings and between corners of respective subsets of the dies;
a plurality of structures disposed within the corner regions, wherein the structures are not a part of any functional transistor, and wherein the structures include test structures, dummy structures, process monitor patterns, alignment marks, or overlay marks;
a plurality of electrical interconnection elements that electrically interconnect the dies in the array with one another; and
a second seal ring that surrounds the array of dies, the first seal rings, and the structures in the top view;
wherein:
at least some of the first seal rings include a plurality of first openings;
the second seal ring includes a second opening;
a first subset of the electrical interconnection elements extend outside of the second seal ring through the second opening;
the first subset of the electrical interconnection elements have diced-off end portions; and
a second subset of the electrical interconnection elements are diagonally oriented in the top view such that they interconnect dies that are disposed diagonally with respect to one another.
2 . The device of claim 1 , wherein none of the corner regions contain any functional transistors.
3 . The device of claim 1 , wherein:
the electrical interconnection elements extend through the first openings to electrically interconnect the dies in the array;
the first seal rings or the second seal ring includes a respective vertical stack of metal lines and vias disposed between the metal lines vertically;
the first seal rings or the second seal ring includes a respective set of conductive pads disposed over the vertical stack of metal lines and vias; and
the first openings and the second opening correspond to openings in one of the metal lines or openings in the conductive pads.
4 . The device of claim 1 , wherein:
the plurality of electrical interconnection elements electrically interconnect a first subset of the dies in the array with one another; and
a second subset of the dies in the array have none of the electrical interconnection elements disposed directly therebetween.
5 . The device of claim 1 , further comprising a circuit formed over the substrate;
wherein:
the circuit is located outside of the second seal ring in the top view; and
the subset of the electrical interconnection elements electrically couple the circuit to the array of dies.
6 . The device of claim 1 , wherein:
the array includes M number of rows extending in a first direction and N number of columns extending in a second direction, and wherein M and N are integers greater than 2;
a third subset of the electrical interconnection elements extend in the first direction to electrically interconnect the dies together in each of the rows; and
a fourth subset of the electrical interconnection elements extend in the second direction to electrically interconnect the dies together in each of the columns.
7 . The device of claim 6 , wherein:
at least one electrical interconnection element of a fifth subset of the electrical interconnection elements includes a first segment that extends in the first direction and a second segment that extends in the second direction in the top view, thereby interconnecting dies from different columns and different rows together.
8 . The device of claim 1 , wherein:
the device is a wafer-level structure;
an entirety of the array of dies is surrounded by the second seal ring in the top view; and
the wafer-level structure contains no other dies other than the array of dies.
9 . The device of claim 1 , wherein:
the device is a wafer-level structure that contains dies outside of the second seal ring; and
the dies surrounded by the second seal ring constitute over 50% of all dies formed on the wafer-level structure.
10 . The device of claim 9 , wherein each of the dies outside of the second seal ring is surrounded in the top view by no more than a single layer of seal ring.
11 . The device of claim 1 , wherein the dies in the array have identical integrated circuit (IC) layouts.
12 . A device, comprising:
a plurality of dies that contains a plurality of transistors;
a plurality of first seal rings located around different ones of the dies in a top view defined by a first direction and a second direction perpendicular to the first direction;
a plurality of structures disposed within a plurality of regions that are located outside of the first seal rings, wherein the structures include test structures, dummy structures, process monitor patterns, alignment marks, or overlay marks;
a second seal ring that surrounds the plurality of dies, the plurality of first seal rings, and the plurality of structures in the top view; and
a plurality of electrical interconnection elements located between adjacent dies in the top view;
wherein:
at least some of the first seal rings include a plurality of first openings in the top view;
the second seal ring includes a second opening in the top view;
a first subset of the electrical interconnection elements span across the second seal ring in the top view through the second opening;
end portions of the first subset of the electrical interconnection elements are diced-off; and
a second subset of the electrical interconnection elements extends in both the first direction and the second direction.
13 . The device of claim 12 , wherein:
the electrical interconnection elements extend through the first openings to electrically interconnect the adjacent dies.
14 . The device of claim 13 , wherein:
the first subset of the electrical interconnection elements extends through both the second opening and a respective one of the first openings.
15 . The device of claim 12 , wherein:
the plurality of dies are arranged into an array of a first number of columns and a second number of rows;
the device is a wafer-level structure; and
the wafer-level structure contains no other dies other than the dies in the array.
16 . The device of claim 1 , wherein the plurality of structures are disposed within the corner regions defined by four adjacently located dies and include one or more of the test structures, the process monitor patterns, the alignment marks, or the overlay marks.
17 . A device, comprising:
a plurality of dies disposed over a substrate;
a plurality of first seal rings that surround the plurality of dies, respectively, in a top view, wherein at least some of the first seal rings include first openings in the top view;
a second seal ring that surrounds the plurality of first seal rings collectively in the top view, wherein the second seal ring includes a second opening in the top view;
a plurality of structures disposed outside the plurality of first seal ring but within the second seal ring in the top view, wherein the plurality of structures include test structures, process monitor patterns, alignment marks, or overlay marks; and
a plurality of metal lines disposed between pairs of adjacent dies in the plurality of dies in the top view, wherein the metal lines electrically interconnect the adjacent dies together, and
wherein:
a first subset of the metal lines extends outside of the second seal ring through the second opening;
the first subset of the metal lines have diced-off end portions;
a second metal line of the metal lines interconnects a first pair of dies that are diagonally located with respect to one another;
a third metal line of the metal lines interconnects a second pair of dies that are diagonally located with respect to one another; and
the second metal line and the third metal line extend in different directions in the top view.
18 . The device of claim 17 , wherein the first subset of the metal lines further extend through at least one of the first seal rings.
19 . The device of claim 17 , wherein the plurality of dies are arranged into an array having more than two columns and more than two rows.
20 . The device of claim 17 , wherein the device is a wafer-level structure that contains no other dies other than the plurality of dies.