Memory device and fabricating method thereof
A memory device includes a substrate, an oxide layer, and a plurality of spacers. The substrate includes a silicon layer, a nitride layer, and a plurality of isolation trenches. The nitride layer overlies the silicon layer. The plurality of isolation trenches penetrates through the nitride layer and a portion of the silicon layer. The oxide layer fills the plurality of isolation trenches and has a surface that is coplanar with a surface of the nitride layer. The plurality of spacers is encircled in the oxide layer, in which top surfaces of the plurality of spacers are covered by the oxide layer.
1 . A fabricating method of a memory device, comprising:
forming a plurality of isolation trenches in a substrate, wherein the substrate comprises a silicon layer and a first nitride layer;
forming a first oxide layer carpet-covering the first nitride layer and the plurality of isolation trenches;
forming a second nitride layer carpet-covering the first oxide layer;
removing portions of the second nitride layer so that at least a portion of the first oxide layer is exposed and remaining portions of the second nitride layer form a plurality of spacers with their top surfaces lower than a surface of the substrate;
forming a second oxide layer to cover the plurality of spacers to an extent that the surface of the second oxide layer is higher than the surface of the substrate; and
removing portions of the second oxide layer such that the second oxide layer and the substrate are coplanar.
2 . The fabricating method of a memory device of claim 1 , wherein the removing the portions of the second oxide layer is performed by chemical mechanical polishing.
3 . The fabricating method of a memory device of claim 1 , wherein the forming the plurality of isolation trenches comprises:
forming the first nitride layer overlying the silicon layer;
forming a photoresist layer overlying the first nitride layer;
performing a lithography process to remove portions of the photoresist layer;
etching through the first nitride layer and a portion of the silicon layer utilizing remaining portions of the photoresist layer as an etching mask to form the plurality of isolation trenches; and
removing the remaining portions of the photoresist layer.
4 . The fabricating method of a memory device of claim 3 , wherein the etching through the first nitride layer and the portion of the silicon layer is performed by reactive ion etching.
5 . The fabricating method of a memory device of claim 1 , wherein the plurality of isolation trenches are formed such that the plurality of isolation trenches form a first patterned zone and a second patterned zone upon completion of etching, the first patterned zone comprises a plurality of first trenches having first trench widths, the second patterned zone comprises a plurality of second trenches having second trench widths, and the first trench widths are larger than the second trench widths.
6 . The fabricating method of a memory device of claim 1 , wherein the forming the second oxide layer comprises:
depositing the second oxide layer by spin on dielectric deposition process; and
densifying the second oxide layer.
7 . The fabricating method of a memory device of claim 1 , wherein the first nitride layer and the second nitride layer comprise silicon nitride, and the first oxide layer and the second oxide layer comprise silicon oxide.
8 . The fabricating method of a memory device of claim 7 , wherein the removing the portions of the second nitride layer is performed by an etching process that has a high selectivity between silicon nitride and silicon oxide so that the first oxide layer remains substantially identical when the portions of the second nitride layer are etched away.
9 . The fabricating method of a memory device of claim 1 , wherein the forming the second nitride layer is performed by chemical vapor deposition.