Semiconductor structure, dicing method thereof, and memory

1 . A semiconductor structure, comprising:

a first wafer, comprising:

a plurality of first peripheral circuit chips;

a first dicing lane between the first peripheral circuit chips; and

a first mark at an edge of the first wafer,

wherein a pointing direction of the first mark is the same as an extending direction of the first dicing lane, a cleavage plane of the first wafer is parallel to the pointing direction of the first mark, and the pointing direction of the first mark is an extending direction of a line of symmetry of the first wafer;

a second wafer; and

a third wafer comprising a plurality of second peripheral circuit chips and a second mark at an edge of the third wafer,

wherein:

the third wafer, the second wafer, and the first wafer are disposed in a stack, and the second wafer comprises a plurality of memory array chips, and

an included angle between a pointing direction of the second mark and an extending direction of a second dicing lane, between the second peripheral circuit chips, is α, where 0°<α<90°.

2 . The semiconductor structure of claim 1 , wherein:

the third wafer further comprises the second dicing lane arranged between the second peripheral circuit chips, and

an extending direction of the second dicing lane is the same as the extending direction of the first dicing lane.

3 . The semiconductor structure of claim 2 , wherein:

characteristic sizes of devices in the second peripheral circuit chips are smaller than characteristic sizes of devices in the first peripheral circuit chips, and

the pointing direction of the second mark is an extending direction of a line of symmetry of the third wafer.

4 . The semiconductor structure of claim 2 , wherein:

the pointing direction of the second mark is an extending direction of a line of symmetry of the third wafer.

5 . The semiconductor structure of claim 2 , wherein the third wafer is located between the first wafer and the second wafer.

6 . The semiconductor structure of claim 2 , wherein the second wafer is located between the first wafer and the third wafer.

7 . The semiconductor structure of claim 1 , wherein the memory array chips comprise three-dimensional NAND memory array chips.

8 . A method of dicing a semiconductor structure, comprising:

providing a semiconductor structure to be diced,

wherein the semiconductor structure to be diced comprises a first wafer, a second wafer, and a third wafer,

wherein the first wafer comprises a plurality of first peripheral circuit chips, a first dicing lane between the first peripheral circuit chips, and a first mark at an edge of the first wafer, a pointing direction of the first mark is the same as an extending direction of the first dicing lane, and a cleavage plane of the first wafer is parallel to the pointing direction of the first mark,

wherein the second wafer and the first wafer are disposed in a stack, and the second wafer comprises a plurality of memory array chips,

wherein the pointing direction of the first mark is an extending direction of a line of symmetry of the first wafer, and

wherein the third wafer comprises a plurality of second peripheral circuit chips and a second mark at an edge of the third wafer, an included angle between a pointing direction of the second mark and an extending direction of a second dicing lane, between the second peripheral circuit chips, being α, where 0°<α<90°;

dicing the first dicing lane from a side of the first wafer away from the second wafer; and

stretching the semiconductor structure to be diced, such that the cleavage plane of the first wafer extends to the second wafer.

9 . The method of claim 8 , wherein dicing the first dicing lane of the first wafer from the side of the first wafer away from the second wafer comprises:

dicing the first dicing lane of the first wafer from the side of the first wafer away from the second wafer by using a laser dicing process.

10 . The method of claim 8 , wherein;

the third wafer comprises the second dicing lane arranged between the second peripheral circuit chips, and

an extending direction of the second dicing lane is the same as the extending direction of the first dicing lane.

11 . The method of claim 10 , wherein:

characteristic sizes of devices in the second peripheral circuit chips are smaller than characteristic sizes of devices in the first peripheral circuit chips,

the pointing direction of the second mark is an extending direction of a line of symmetry of the third wafer, and

stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer extends to the second wafer comprises:

stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer extends to the second wafer and the third wafer.

12 . The method of claim 10 , wherein:

the pointing direction of the second mark is an extending direction of a line of symmetry of the third wafer,

the second wafer is located between the first wafer and the third wafer, and

the method further comprises:

dicing the second dicing lane from a side of the third wafer away from the second wafer while dicing the first dicing lane from the side of the first wafer away from the second wafer.

13 . The method of claim 10 , wherein:

the pointing direction of the second mark is an extending direction of a line of symmetry of the third wafer.

14 . The method of claim 8 , wherein stretching the semiconductor structure to be diced comprises:

stretching the semiconductor structure to be diced along a direction perpendicular to the cleavage plane of the first wafer.

15 . The method of claim 8 , wherein providing the semiconductor structure to be diced comprises:

providing the first wafer comprising the plurality of first peripheral circuit chips;

providing the second wafer comprising the plurality of memory array chips; and

bonding the first wafer to the second wafer to form the semiconductor structure to be diced.

16 . A method of forming a memory, comprising:

providing a semiconductor structure to be diced,

wherein the semiconductor structure to be diced comprises a first wafer, a second wafer, and a third wafer,

wherein the first wafer comprises a plurality of first peripheral circuit chips, a first dicing lane between the first peripheral circuit chips, and a first mark at an edge of the first wafer, a pointing direction of the first mark is the same as an extending direction of the first dicing lane, and a cleavage plane of the first wafer is parallel to the pointing direction of the first mark,

wherein the second wafer and the first wafer are disposed in a stack, and the second wafer comprises a plurality of memory array chips,

wherein the pointing direction of the first mark is an extending direction of a line of symmetry of the first wafer, and

wherein the third wafer comprises a plurality of second peripheral circuit chips and a second mark at an edge of the third wafer, the second mark indicating a direction along a line of symmetry of the third wafer, and the line of symmetry of the third wafer being non-collinear with the line of symmetry of the first wafer;

dicing the first dicing lane from a side of the first wafer away from the second wafer; and

stretching the semiconductor structure to be diced, such that the cleavage plane of the first wafer extends to the second wafer.

17 . The method of claim 16 , wherein dicing the first dicing lane of the first wafer from the side of the first wafer away from the second wafer comprises:

dicing the first dicing lane of the first wafer from the side of the first wafer away from the second wafer by using a laser dicing process.

18 . The method of claim 16 , wherein:

the third wafer comprises a second dicing lane arranged between the second peripheral circuit chips, and

an extending direction of the second dicing lane is the same as the extending direction of the first dicing lane.

19 . The method of claim 18 , wherein:

an included angle between a pointing direction of the second mark and the extending direction of the second dicing lane is a, 0°<a<90°, and characteristic sizes of devices in the second peripheral circuit chips are smaller than characteristic sizes of devices in the first peripheral circuit chips,

the pointing direction of the second mark is an extending direction of the line of symmetry of the third wafer, and

stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer extends to the second wafer comprises:

stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer extends to the second wafer and the third wafer.

20 . The method of claim 18 , wherein:

the pointing direction of the second mark is an extending direction of the line of symmetry of the third wafer.