Integrated circuit having a routable leadframe

1 . A method, comprising:

depositing a metal layer on a carrier, the metal layer comprising metal traces, metal pillars disposed on the metal traces, and leads;

patterning a photoresist material layer on the leads;

forming a dielectric layer over the metal layer, surfaces of the metal pillars being exposed from a first surface of the dielectric layer;

removing the photoresist material layer from the leads; removing the carrier;

attaching a die to the first surface of the dielectric layer, the die including electrical contacts on a surface of the die that contacts the dielectric layer, the electrical contacts being aligned with and electrically connecting with the exposed surfaces of the metal pillars;

attaching a bonding wire from the die to at least one of the metal traces and/or at least one of the leads; and

forming a mold compound over the die, the dielectric layer, and the metal layer, wherein surfaces of the metal traces are exposed from a second surface of the dielectric layer opposite the first surface and are not covered by the mold compound.

2 . The method of claim 1 , wherein depositing the metal layer on the carrier includes providing a metal carrier, patterning and developing a first photoresist material layer on the metal carrier to expose first openings in the first photoresist material layer, electroplating the metal traces on the metal carrier in the first openings of the first photoresist material layer, and stripping the first photoresist material layer via a first etching process.

3 . The method of claim 2 , wherein depositing the metal layer on the carrier further includes patterning and developing a second photoresist material layer on the metal carrier to expose second openings in the second photoresist material layer, electroplating the metal pillars on the metal traces in the second openings of the second photoresist material layer, and stripping the second photoresist material layer via a second etching process.

4 . The method of claim 3 , wherein patterning the photoresist material layer on the leads includes depositing a third photoresist material layer over the metal layer and patterning and developing the third photoresist material layer to expose all portions of the metal layer except portions of the leads.

5 . The method of claim 4 , wherein forming the dielectric layer over the metal layer includes compression molding the dielectric layer over the metal layer and grinding the dielectric layer to expose the surfaces of the metal pillars and to expose the third photoresist material layer.

6 . The method of claim 5 , wherein removing the photoresist material layer from the leads includes stripping the third photoresist material layer via a third etching process.

7 . The method of claim 1 , wherein removing the carrier includes dislodging the carrier from the dielectric layer and the metal layer via a chemical etch process and a mechanical process.

8 . The method of claim 1 , further comprising bending the leads in a direction away from the die to facilitate connection to a circuit board.

9 . A method of fabricating an integrated circuit, the method comprising:

providing a metal carrier, the metal carrier having a metal carrier layer deposited on a surface of the metal carrier;

depositing a metal layer on the metal carrier layer, the metal layer comprising metal traces, metal pillars disposed on the metal traces, and leads;

patterning a photoresist material layer on the leads;

forming a dielectric layer over the metal layer, surfaces of the metal pillars being exposed from a first surface of the dielectric layer;

removing the photoresist material layer from the leads;

removing the metal carrier;

attaching a die to the first surface of the dielectric layer, the die including electrical contacts on a surface of the die that contacts the dielectric layer, the electrical contacts being aligned with and electrically connecting with the exposed surfaces of the metal pillars;

attaching a bonding wire from the die to at least one of the metal traces and/or at least one of the leads;

forming a mold compound over the die, the dielectric layer, and the metal layer; and

bending the leads in a direction away from the die to facilitate connection to a circuit board, wherein surfaces of the metal traces are exposed from a second surface of the dielectric layer opposite the first surface and are not covered by the mold compound.

10 . The method of claim 9 , wherein depositing the metal layer on the metal carrier layer includes patterning and developing a first photoresist material layer on the metal carrier layer to expose first openings in the first photoresist material layer, electroplating the metal traces on the metal carrier layer in the first openings of the first photoresist material layer, and stripping the first photoresist material layer via a first etching process.

11 . The method of claim 10 , wherein depositing the metal layer on the metal carrier layer further includes patterning and developing a second photoresist material layer on the metal carrier layer to expose second openings in the second photoresist material layer, electroplating the metal pillars on the metal traces in the second openings of the second photoresist material layer, and stripping the second photoresist material layer via a second etching process.

12 . The method of claim 11 , wherein patterning the photoresist material layer on the leads includes depositing a third photoresist material layer over the metal layer and patterning and developing the third photoresist material layer to expose all portions of the metal layer except portions of the leads.

13 . The method of claim 12 , wherein forming the dielectric layer over the metal layer includes compression molding the dielectric layer over the metal layer and grinding the dielectric layer to expose the surfaces of the metal pillars and to expose the third photoresist material layer.

14 . The method of claim 13 , wherein removing the photoresist material layer from the leads includes stripping the third photoresist material layer via a third etching process.

15 . An electronic device, comprising:

a dielectric layer;

a metal layer embedded in the dielectric layer, the metal layer including leads, metal traces, and metal pillars, surfaces of the metal pillars being exposed from a first surface of the dielectric layer;

a die attached to the first surface of the dielectric layer, the die including electrical contacts on a first surface of the die that contacts the dielectric layer, the electrical contacts being aligned with and electrically connecting with the exposed surfaces of the metal pillars;

bonding wires that extend from pins on a second surface of the die opposite the first surface that contacts the dielectric layer to at least one of the metal traces and/or at least one of the leads; and

a mold compound over the dielectric layer, the metal layer, and the die,

wherein surfaces of the metal traces are exposed from a second surface of the dielectric layer opposite the first surface and are not covered by the mold compound.

16 . The electronic device of claim 15 , wherein the leads are bended in a direction that facilitates a connection to a circuit board.

17 . The electronic device of claim 15 , wherein the metal pillars are disposed on the metal traces.