IP Library Granted Patent US 12707998
Granted Patent B2
US 12707998 · App. 18/243,290 · Granted Aug 11, 2026

Semiconductor device

Inventor: Fumiyoshi Kawashiro (Tokyo, JP)
Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
H10W70/481H10W90/756H10W70/415H10W72/073H10W72/07331H10W72/07336H10W72/07354H10W72/075H10W72/07533H10W72/347H10W72/352H10W72/5449H10W72/552H10W72/5522H10W72/5525H10W72/555H10W72/865H10W72/884H10W72/926H10W72/944H10W74/01H10W74/114H10W90/736
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Quick Facts
Patent No.
US 12707998
App. No.
18/243,290
Granted
Aug 11, 2026
Kind
B2
Abstract

According to one embodiment, there is provided a semiconductor device including a chip, a drain electrode arranged on a first surface of the chip, a source electrode arranged on a second surface provided on a back side of the first surface of the chip and having a front surface on a device bottom surface, a gate electrode having a front surface on the device bottom surface, and a wire connecting a first region of the gate electrode to a second region on the second surface of the chip.

Claims (22)

1 . A semiconductor device comprising:

a chip;

a drain electrode arranged on a first surface of the chip;

a source electrode arranged on a second surface provided on a back side of the first surface of the chip and having a front surface on a device bottom surface;

a gate electrode having a front surface on the device bottom surface; and

a wire connecting a first region of the gate electrode to a second region on the second surface of the chip, wherein

the drain electrode and the gate electrode are formed with a single lead frame with a dented head, and

the first region of the gate electrode is located at an inner surface of the dented head.

2 . The semiconductor device according to claim 1 , wherein the drain electrode has a flat plate portion on a side of the second surface of the chip, and the gate electrode has a flat plate portion at the same height as the flat plate portion of the drain electrode.

3 . The semiconductor device according to claim 2 , wherein the gate electrode has the first region in a flat plate portion of the gate electrode, the first region being connected to the wire.

4 . The semiconductor device according to claim 1 , wherein the source electrode and the drain electrode are bonded to the chip with solder.

5 . The semiconductor device according to claim 1 , wherein the source electrode and the drain electrode are bonded to the chip with a pressure-sintered material.

6 . The semiconductor device according to claim 1 , wherein the semiconductor device is sealed in a package of a source-down structure in which the source electrode is provided on a bottom surface of the package.

7 . A semiconductor device comprising:

a chip;

a drain electrode arranged on a first surface of the chip;

a source electrode arranged on a second surface provided on a back side of the first surface of the chip and having a connection portion and an external exposed portion, the connection portion being connected to the second surface, the external exposed portion being exposed on a side opposite to the connection portion;

a gate electrode being formed by bending a plate-like metal member; and

a wire connecting a first region of the gate electrode to a second region on the second surface of the chip, wherein

the drain electrode and the gate electrode are formed with a single lead frame with a dented head, and

the first region of the gate electrode is located at an inner surface of the dented head.

8 . The semiconductor device according to claim 7 , wherein when viewed from a direction perpendicular to the second surface of the chip, the external exposed portion of the source electrode has a region that overlaps with the second surface of the chip.