Integrated circuit device having active region coupled to conductive patterns on opposite sides of substrate

1 . An integrated circuit (IC) device, comprising:

a substrate having opposite first and second sides;

a plurality of active regions over the first side of the substrate, the plurality of active regions comprising a first active region;

a plurality of gate regions over the plurality of active regions;

a first conductive pattern over and electrically coupled to the first active region;

a first through via structure extending from the second side, through the substrate, to the first side in electrical contact with the first active region; and

a second conductive pattern under the second side of the substrate and electrically coupled to the first through via structure,

wherein

the plurality of gate regions and the plurality of active regions together are configured as a plurality of transistors,

the plurality of transistors comprises a pair of adjacent first transistors on opposite sides of the first active region, and

each first transistor in the pair of adjacent first transistors

is electrically coupled to be in an always-OFF state, or

has the corresponding gate region floating.

2 . The IC device of claim 1 , wherein

the first active region is configured as a resistor structure.

3 . The IC device of claim 1 , wherein

the second conductive pattern comprises a power supply voltage rail.

4 . The IC device of claim 1 , wherein

the first conductive pattern is in a metal-zero layer, and

the second conductive pattern is in a backside metal-zero layer.

5 . The IC device of claim 1 , further comprising:

a second through via structure extending from the second side, through the substrate, to the first side in electrical contact with a second active region among the plurality of active regions,

wherein

the first and second active regions are electrically coupled one to another through at least one of the first conductive pattern or the second conductive pattern,

the plurality of transistors further comprises a pair of adjacent second transistors on opposite sides of the second active region, and

each second transistor in the pair of adjacent second transistors

is electrically coupled to be in the always-OFF state, or

has the corresponding gate region floating.

6 . The IC device of claim 5 , wherein

the plurality of transistors further comprises at least one third transistor between the pair of adjacent first transistors and the pair of adjacent second transistors, and

the at least one third transistor

is electrically coupled to be in the always-OFF state, or

has the corresponding gate region floating.

7 . The IC device of claim 5 , wherein

the plurality of transistors further comprises at least one third transistor between the pair of adjacent first transistors and the pair of adjacent second transistors, and

the at least one third transistor is electrically coupled into a capacitor.

8 . The IC device of claim 7 , wherein

the pair of adjacent first transistors comprises:

one first transistor between the first active region and the at least one third transistor, and having the corresponding gate region floating, and

another first transistor electrically coupled to be in the always-OFF state, and

the pair of adjacent second transistors comprises:

one second transistor between the second active region and the at least one third transistor, and having the corresponding gate region floating, and

another second transistor electrically coupled to be in the always-OFF state.

9 . The IC device of claim 5 , wherein

one first transistor in the pair of adjacent first transistors is immediately adjacent to one second transistor in the pair of adjacent second transistors.

10 . The IC device of claim 5 , further comprising:

a third through via structure extending from the second side, through the substrate, to the first side in electrical contact with a third active region among the plurality of active regions,

wherein

the first active region is between the second active region and the third active region,

the first and second active regions are electrically coupled one to another through one of the first conductive pattern and the second conductive pattern, and

the first and third active regions are electrically coupled one to another through the other of the first conductive pattern and the second conductive pattern.

11 . An integrated circuit (IC) device, comprising:

a plurality of active regions;

a plurality of gate regions over the plurality of active regions, the plurality of gate regions and the plurality of active regions together configured as a plurality of transistors;

a first metal layer over the plurality of active regions;

a second metal layer under the plurality of active regions; and

first and second resistor structures correspondingly comprising first and second active regions among the plurality of active regions,

wherein one of the first metal layer and the second metal layer comprises a conductive pattern electrically coupling the first and second resistor structures.

12 . The IC device of claim 11 , wherein

the plurality of transistors comprises

a pair of adjacent first transistors having a common source/drain region in the first active region of the first resistor structure, and

a pair of adjacent second transistors having a common source/drain region in the second active region of the second resistor structure, and

each of the first and second transistors

is electrically coupled to be in an always-OFF state, or

has the corresponding gate region floating.

13 . The IC device of claim 11 , wherein

the conductive pattern overlaps, among the plurality of gate regions, gate regions of at least two transistors among the plurality of transistors, and

each of the at least two transistors

is electrically coupled to be in an always-OFF state, or

has the corresponding gate region floating, or

is electrically coupled into a capacitor.

14 . The IC device of claim 11 , wherein

the first and second resistor structures are electrically coupled in parallel by

the conductive pattern in the one of the first metal layer and the second metal layer, and

a further conductive pattern in the other of the first metal layer and the second metal layer.

15 . The IC device of claim 11 , wherein

the first metal layer comprises the conductive pattern electrically coupling corresponding first ends of the first and second resistor structures,

the second metal layer comprises a further conductive pattern electrically coupled to a second end of one of the first and second resistor structures,

the further conductive pattern overlaps the one of the first and second resistor structures and the conductive pattern, and

in a direction along which the plurality of gate regions extend, the further conductive pattern has a greater dimension than the conductive pattern.

16 . The IC device of claim 11 , wherein

the first metal layer comprises a further conductive pattern electrically coupled to a first end of one of the first and second resistor structures,

the second metal layer comprises the conductive pattern electrically coupling corresponding second ends of the first and second resistor structures,

the conductive pattern overlaps the first and second resistor structures, and the further conductive pattern, and

in a direction along which the plurality of gate regions extend, the conductive pattern has a greater dimension than the further conductive pattern.

17 . An integrated circuit (IC) device, comprising:

a substrate having, in a thickness direction of the substrate, opposite first and second sides; and

a plurality of resistor cells over the first side of the substrate, each of the plurality of resistor cells comprising:

a pair of transistors, and

a resistor structure comprising a common source/drain of the pair of transistors,

wherein the resistor structures of the plurality of resistor cells are electrically coupled to each other in series or in parallel by one or more conductive patterns on the second side of the substrate.

18 . The IC device of claim 17 , wherein

in at least one cell of the plurality of resistor cells,

the pair of transistors is a pair of first transistor,

the resistor structure is a first resistor structure,

the at least one cell of the plurality of resistor cells further comprises:

a pair of second transistors, and

a second resistor structure comprising a common source/drain of the pair of second transistors, and

over one of the first side and the second side of the substrate, an end of the first resistor structure is electrically coupled to an end of the second resistor structure.

19 . The IC device of claim 18 , wherein

the at least one cell of the plurality of resistor cells further comprises:

a third transistor, and

a third resistor structure comprising a source/drain of the third transistor, and

over the other of the first side and the second side of the substrate, a further end of the first resistor structure is electrically coupled to an end of the third resistor structure.

20 . The IC device of claim 17 , further comprising:

a through via structure extending from the second side, through the substrate, to the first side, to electrically couple the resistor structure of a resistor cell of the plurality of resistor cells to a conductive pattern of the one or more conductive patterns on the second side of the substrate.