Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a first dielectric layer, a first die, a second die, a first molding, and a second molding. The first die is disposed under the first dielectric layer, and has a first surface facing the first dielectric layer and a second surface opposite to the first surface. The second die is disposed over the first dielectric layer, and has a third surface facing the first dielectric layer and a fourth surface opposite to the third surface. The first molding encapsulates the first die. The second molding is disposed over the first die and the first dielectric layer. The first surface of the first die and the third surface of the second die are in contact with the first dielectric layer. The fourth surface of the second die is partially exposed through the second molding and partially covered by the second molding.
1 . A semiconductor structure comprising:
a first dielectric layer;
a first die disposed under the first dielectric layer and having a first surface facing the first dielectric layer and a second surface opposite to the first surface;
a second die disposed over the first dielectric layer and having a third surface facing the first dielectric layer and a fourth surface opposite to the third surface, wherein the second die includes a sensor;
a first molding encapsulating the first die; and
a second molding disposed over the first die and the first dielectric layer,
wherein the first surface of the first die and the third surface of the second die are in contact with the first dielectric layer, the first molding contacts an entirety of the second surface of the first die, an outer edge of the first dielectric layer is level with an outer edge of the second molding and an outer edge of the first molding, and the fourth surface of the second die is partially exposed through the second molding and partially covered by the second molding, wherein a portion of the fourth surface of the second die over the sensor is exposed.
2 . The semiconductor structure of claim 1 , wherein the first die comprises a first sidewall between the first surface and the second surface, and the first sidewall and the second surface are in contact with the first molding.
3 . The semiconductor structure of claim 1 , further comprising a second dielectric layer under the first die, wherein the first die is separated from the second dielectric layer by the first molding.
4 . The semiconductor structure of claim 3 , further comprising a first interconnect structure in the first dielectric layer and electrically connected to the first die and the second die.
5 . The semiconductor structure of claim 4 , further comprising a second interconnect structure in the second dielectric layer and electrically connected to the first interconnect structure.
6 . The semiconductor structure of claim 5 , further comprising a conductive via extending through the first molding and electrically connecting the first interconnect structure and the second interconnect structure.
7 . The semiconductor structure of claim 1 , wherein a thickness of the second molding is greater than a thickness of the second die.
8 . The semiconductor structure of claim 1 , wherein the second molding is free of an interconnect structure.
9 . A semiconductor structure comprising:
a first die and a second die, wherein the first die has a first surface and a second surface opposite to the first surface, wherein the second die includes a sensor;
a dielectric layer and an interconnect structure between the first die and the second die, wherein the first die and the second die are electrically connected by the interconnect structure, wherein the dielectric layer has a constant width, wherein the first surface of the first die is in contact with the dielectric layer, wherein the second die has a bottom surface in contact with the dielectric layer, wherein the dielectric layer is solid from an uppermost surface of the dielectric layer to a lowermost surface of the dielectric layer;
a first molding in contact with a sidewall of the first die, wherein an entirety of the second surface of the first die is in contact with the first molding; and
a second molding in contact with sidewalls of the second die,
wherein a first portion of a top surface of the second die is covered by the second molding, and a second portion of the top surface of the second die is exposed through the second molding, wherein the second portion is aligned with the sensor of the second die.
10 . The semiconductor structure of claim 9 , wherein the second portion of the top surface of the second die is surrounded by the first portion of the top surface of the second die.
11 . A package comprising:
a first semiconductor die, the first semiconductor die comprising a first insulating layer;
a second semiconductor die, the second semiconductor die comprising a second insulating layer, wherein the second semiconductor die includes a sensor;
a first redistribution structure between the first semiconductor die and the second semiconductor die, the first redistribution structure comprising conductive features that electrically couple the first semiconductor die to the second semiconductor die, the first redistribution structure contacting the first insulating layer of the first semiconductor die and the second insulating layer of the second semiconductor die, the first redistribution structure having a constant width, wherein the first redistribution structure is free of solder and underfill, wherein no active devices are positioned between a first surface of the first redistribution structure and a second surface of the first redistribution structure, the first surface of the first redistribution structure facing the first semiconductor die, the second surface of the first redistribution structure facing the second semiconductor die;
a first encapsulant surrounding the first semiconductor die, the first encapsulant completely covering a first surface and sidewalls of the first semiconductor die, the first surface of the first semiconductor die facing away from the first redistribution structure; and
a second encapsulant surrounding the second semiconductor die, wherein the second encapsulant only partially covers a lateral surface of the second semiconductor die, wherein a first portion of the lateral surface of the second semiconductor die is exposed through the second encapsulant, wherein the first portion is aligned over the sensor, the lateral surface of the second semiconductor die being opposite to the first redistribution structure.
12 . The package of claim 11 , wherein a center region of the lateral surface of the second semiconductor die is exposed through the second encapsulant.
13 . The package of claim 11 further comprising:
a second redistribution structure on an opposing side of the first semiconductor die as the first redistribution structure; and
a conductive via extending through the first encapsulant, wherein the conductive via electrically couples the conductive features of the first redistribution structure to conductive features of the second redistribution structure.
14 . The package of claim 13 , wherein the first encapsulant extends between a lateral surface of the first semiconductor die and the second redistribution structure.
15 . The package of claim 13 , wherein the first encapsulant, the second encapsulant, and the first redistribution structure are co-terminous.
16 . The package of claim 13 , wherein a sidewall of the second encapsulant extends from a lateral surface of the second encapsulant to the lateral surface of the second semiconductor die.
17 . The semiconductor structure of claim 1 , wherein the first dielectric layer is continuous from an upper surface of the first dielectric layer to a lower surface of the first dielectric layer.
18 . The semiconductor structure of claim 1 , wherein a sidewall of the first dielectric layer is continuous and flat from an upper surface of the first dielectric layer to a lower surface of the first dielectric layer.
19 . The semiconductor structure of claim 9 , wherein a sidewall of the dielectric layer is continuous and flat from an upper surface of the dielectric layer to a lower surface of the dielectric layer.
20 . The package of claim 13 , wherein the second redistribution structure and the second encapsulant are co-terminous.