Semiconductor device
A semiconductor package includes a first redistribution structure having at least one first redistribution layer and at least one first insulating layer that are alternately stacked, a semiconductor chip electrically connected to the first redistribution structure, a second insulating layer disposed above the semiconductor chip and having an opening, a pad electrically connected to the first redistribution structure, disposed on the second insulating layer, and overlapping the opening, a pad surface layer disposed on a first region of an upper surface of the pad to overlap the opening, the pad surface layer formed of a first conductive material different from a second conductive material forming the pad. The pad has an anchor portion protruding from a second region of the upper surface of the pad. The anchor portion protrudes to a position higher than that of a lower surface of the pad surface layer.
1 . A semiconductor package comprising:
a first redistribution structure having at least one first redistribution layer and at least one first insulating layer that are alternately stacked;
a semiconductor chip electrically connected to the first redistribution structure;
a second insulating layer disposed above the semiconductor chip and having an opening extending through the second insulating layer;
a pad electrically connected to the first redistribution structure, disposed below the second insulating layer, and overlapping the opening in a vertical direction; and
a pad surface layer disposed on a first region of an upper surface of the pad to overlap the opening in the vertical direction, the pad surface layer formed of a first conductive material different from a second conductive material forming the pad,
wherein the pad has an anchor portion protruding from a second region of the upper surface of the pad that does not overlap the opening in the vertical direction, and
the anchor portion protrudes vertically into the second insulating layer to a position higher than that of a lower surface of the pad surface layer.
2 . The semiconductor package of claim 1 , wherein a portion of the second insulating layer extends into a space between the anchor portion and the pad surface layer.
3 . The semiconductor package of claim 1 , wherein the anchor portion surrounds the pad surface layer in a horizontal direction.
4 . The semiconductor package of claim 3 , wherein the anchor portion comprises a plurality of anchor sub-portions and a portion of the second insulating layer extends into between anchor sub-portions to surround the pad surface layer.
5 . The semiconductor package of claim 4 , wherein each of the anchor sub-portions protrudes into the second insulating layer for a distance that is longer than a width of each of the anchor sub-portions.
6 . The semiconductor package of claim 1 , wherein
the pad surface layer includes a first pad surface layer and a second pad surface layer,
the first pad surface layer and the second pad surface layer are each formed of different conductive materials, and
the first pad surface layer is disposed between the second pad surface layer and the pad.
7 . The semiconductor package of claim 6 , wherein
the pad is formed of copper (Cu) or an alloy of copper,
the first pad surface layer is formed of nickel (Ni) or an alloy of nickel, and
the second pad surface layer is formed of gold (Au) or an alloy of gold.
8 . The semiconductor package of claim 1 , wherein the second insulating layer contains a build-up film.
9 . The semiconductor package of claim 1 , wherein a side surface and a first portion of an upper surface of the pad surface layer are in contact with the second insulating layer, and a second portion of the upper surface of the pad surface layer is exposed by the opening of the second insulating layer.
10 . The semiconductor package of claim 9 , further comprising:
an additional second insulating layer having a portion in contact with the lower surface of the pad, the additional second insulating layer containing a build-up film,
wherein the additional second insulating layer is in contact with a lower surface of the second insulating layer.
11 . The semiconductor package of claim 1 , further comprising:
an encapsulant disposed between the first redistribution structure and the second insulating layer to encapsulate the semiconductor chip.
12 . The semiconductor package of claim 11 , wherein
the pad has a conductive via protruding from the lower surface of the pad and overlapping the pad surface layer in a vertical direction, and
the conductive via passes through the encapsulant.
13 . The semiconductor package of claim 1 , wherein the pad is disposed at a lower surface of the second insulating layer.
14 . A semiconductor package comprising:
a first redistribution structure having at least one first redistribution layer and at least one first insulating layer that are alternately stacked;
a semiconductor chip disposed above the first redistribution structure;
a second insulating layer disposed above the semiconductor chip and having an opening at an upper surface of the second insulating layer;
a pad electrically connected to the first redistribution structure, disposed below the second insulating layer, and overlapping the opening in a vertical direction;
a first pad surface layer disposed on a first region of an upper surface of the pad to overlap the opening, the first pad surface layer formed of nickel (Ni) or an alloy of nickel;
a second pad surface layer disposed on an upper surface of the first pad surface layer and overlapping the opening, the second pad surface layer formed of gold (Au) or an alloy of gold; and
an encapsulant disposed between the first redistribution structure and the second insulating layer, the encapsulant encapsulating the semiconductor chip,
wherein the pad has an anchor portion protruding into the second insulating layer from a second region of the upper surface of the pad that does not overlap the opening in a vertical direction,
the anchor portion protrudes to a position higher than that of a lower surface of the first pad surface layer, and
a portion of the second insulating layer is disposed in a space between the anchor portion and the first pad surface layer.
15 . The semiconductor package of claim 14 , further comprising:
an additional second insulating layer disposed between the second insulating layer and the encapsulant, the additional second insulating layer in contact with the second insulating layer, the additional second insulating layer containing an insulating material different from that of the encapsulant; and
a second redistribution layer disposed on the additional second insulating layer,
wherein a redistribution line of the second redistribution layer crosses underneath a lower side of the pad.
16 . A semiconductor package comprising:
a first redistribution structure having at least one first redistribution layer and at least one first insulating layer that are alternately stacked;
a semiconductor chip electrically connected to the first redistribution structure;
a second insulating layer disposed above the semiconductor chip and having an opening;
a pad electrically connected to the first redistribution structure, disposed below the second insulating layer, and overlapping the opening;
a pad surface layer disposed on a first region of an upper surface of the pad to overlap the opening, the pad surface layer formed of a first conductive material different from a second conductive material forming the pad;
an additional second insulating layer having a portion disposed on a lower surface of the pad; and
a second redistribution layer disposed on the additional second insulating layer,
wherein the pad has an anchor portion protruding from a second region of the upper surface of the pad,
the anchor portion protrudes to a position higher than that of a lower surface of the pad surface layer,
a redistribution line of the second redistribution layer crosses under a side surface of the pad.
17 . The semiconductor package of claim 16 , wherein a width of the pad surface layer is narrower than a width of the pad.
18 . The semiconductor package of claim 17 , wherein the pad surface layer includes:
a second pad surface layer containing gold (Au) or an alloy of gold; and
a first pad surface layer containing nickel (Ni) or an alloy of nickel, the first pad surface layer disposed between the second pad surface layer and the pad.
19 . The semiconductor package of claim 18 , wherein
the second insulating layer contains a build-up film, and
a side surface and a first portion of an upper surface of the second pad surface layer are in contact with the second insulating layer, and a second portion of the upper surface of the pad surface layer is exposed by the opening of the second insulating layer.
20 . The semiconductor package of claim 19 , further comprising:
an encapsulant disposed between the first redistribution structure and the second insulating layer, the encapsulant encapsulating the semiconductor chip,
wherein the conductive via passes through the encapsulant.
21 . The semiconductor package of claim 16 , wherein the pad is disposed at a lower surface of the second insulating layer,
the second region of the upper surface of the pad does not overlap the opening in a vertical direction, and
the anchor portion protrudes vertically into the second insulating layer to a position higher than that of the lower surface of the pad surface layer.