Semiconductor package and manufacturing method thereof
A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.
1 . A semiconductor package comprising:
a substrate comprising:
a first substrate side;
a second substrate side opposite the first substrate side;
a recess portion in the first substrate side and extending toward the second substrate side to a recess floor, wherein the recess portion is laterally between a first portion of the first substrate side and a second portion of the first substrate side, and wherein the recess portion is vertically between the recess floor and a plane extending between the first portion and the second portion of the first substrate side;
a dielectric structure having a first dielectric side, a second dielectric side, and a lateral dielectric side extending between the first dielectric side and the second dielectric side, wherein the recess portion extends from the first dielectric side to the second dielectric side and is defined, at least partially, by the lateral dielectric side;
a first conductive pattern at the first dielectric side;
a second conductive pattern at the second dielectric side; and
a conductive via that passes through the dielectric structure and electrically connects the first conductive pattern and the second conductive pattern;
a first semiconductor die coupled to a first portion of the first conductive pattern at the first portion of the first substrate side;
a second semiconductor die coupled to a second portion of the first conductive pattern at the second portion of the first substrate side;
an electronic component positioned in the recess portion of the substrate; and
an encapsulating material that contacts the lateral dielectric side, covers at least lateral sides of the electronic component, and extends vertically above at least a portion of the first conductive pattern.
2 . The semiconductor package of claim 1 , wherein an entirety of the electronic component is between the first substrate side and the second substrate side.
3 . The semiconductor package of claim 1 , wherein the electronic component comprises a capacitor.
4 . The semiconductor package of claim 1 , wherein the substrate comprises a conductive layer in the recess portion.
5 . The semiconductor package of claim 4 , wherein the electronic component is electrically coupled to the conductive layer of the recess portion.
6 . The semiconductor package of claim 1 , comprising a solder resist on the first substrate side, wherein:
the first semiconductor die is coupled to the first portion of the first conductive pattern through a first opening in the solder resist, and
the second semiconductor die is coupled to the second portion of the first conductive pattern through a second opening in the solder resist.
7 . The semiconductor package of claim 1 , wherein the electronic component is electrically coupled to the first semiconductor die and the second semiconductor die.
8 . The semiconductor package of claim 1 , comprising a volume that laterally surrounds the electronic component, wherein the volume is filled by the encapsulating material.
9 . A semiconductor package comprising:
a substrate comprising:
a first substrate side;
a second substrate side opposite the first substrate side;
a recess portion in the first substrate side and extending toward the second substrate side;
a dielectric structure having a first dielectric side, a second dielectric side, and lateral dielectric sides extending between the first dielectric side and the second dielectric side, wherein the recess portion extends from the first dielectric side to the second dielectric side between the lateral dielectric sides;
a first conductive pattern at the first dielectric side;
a second conductive pattern at the second dielectric side; and
a conductive via that passes through the dielectric structure and electrically connects the first conductive pattern and the second conductive pattern;
a solder resist on the first substrate side;
a first semiconductor die coupled to a first portion of the first conductive pattern through a first opening in the solder resist, wherein the first portion of the first conductive pattern is laterally offset from the recess portion in a first direction;
a second semiconductor die coupled to a second portion of the first conductive pattern through a second opening in the solder resist, wherein the second portion of the first conductive pattern is laterally offset from the recess portion in a second direction opposite the first direction;
an electronic component positioned in the recess portion of the substrate; and
an encapsulating material that contacts the lateral dielectric sides, covers at least lateral sides of the electronic component, and extends vertically above at least a portion of the first dielectric side.
10 . The semiconductor package of claim 9 , wherein the encapsulating material contacts the solder resist.
11 . The semiconductor package of claim 9 , comprising a conductive layer in the recess portion, wherein the electronic component is electrically coupled to the conductive layer of the recess portion.
12 . The semiconductor package of claim 9 , wherein the electronic component is electrically coupled to the first semiconductor die and the second semiconductor die.
13 . A method of manufacturing a semiconductor package, the method comprising:
providing a substrate comprising:
a first substrate side;
a second substrate side opposite the first substrate side;
a recess portion in the first substrate side and extending toward the second substrate side to a recess floor, wherein the recess portion is laterally between a first portion of the first substrate side and a second portion of the first substrate side, and wherein the recess portion is vertically between the recess floor and a plane extending between the first portion and the second portion of the first substrate side;
a dielectric structure having a first dielectric side, a second dielectric side, and a lateral dielectric side extending between the first dielectric side and the second dielectric side, wherein the recess portion extends from the first dielectric side to the second dielectric side and is defined, at least partially, by the lateral dielectric side;
a first conductive pattern at the first dielectric side;
a second conductive pattern at the second dielectric side; and
a conductive via that passes through the dielectric structure and electrically connects the first conductive pattern and the second conductive pattern;
providing a first semiconductor die on a first portion of the first conductive pattern at the first portion of the first substrate side;
providing a second semiconductor die on a second portion of the first conductive pattern at the second portion of the first substrate side;
providing an electronic component in the recess portion of the substrate; and
providing an encapsulating material that contacts the lateral dielectric side, covers at least lateral sides of the electronic component, and extends vertically above at least a portion of the first conductive pattern.
14 . The method of manufacturing the semiconductor package of claim 13 , wherein an entirety of the electronic component is provided between the first substrate side and the second substrate side.
15 . The method of manufacturing the semiconductor package of claim 13 , wherein the electronic component comprises a capacitor.
16 . The method of manufacturing the semiconductor package of claim 13 , wherein the substrate comprises a conductive layer in the recess portion.
17 . The method of manufacturing the semiconductor package of claim 16 , wherein the electronic component is electrically coupled to the conductive layer of the recess portion.
18 . The method of manufacturing the semiconductor package of claim 13 , comprising providing a solder resist on the first substrate side, wherein:
the first semiconductor die is coupled to the first portion of the first conductive pattern through a first opening in the solder resist, and
the second semiconductor die is coupled to the second portion of the first conductive pattern through a second opening in the solder resist.
19 . The method of manufacturing the semiconductor package of claim 13 , wherein the electronic component is electrically coupled to the first semiconductor die and the second semiconductor die.
20 . The method of manufacturing the semiconductor package of claim 13 , wherein the encapsulating material is provided in a volume that laterally surrounds the electronic component.