Semiconductor package having first pad and second pad
A semiconductor package includes a first semiconductor chip stacked on a second semiconductor chip. The first semiconductor chip includes a first substrate, a first insulating layer on a lower surface of the first substrate, and a first pad exposed through the first insulating layer. The second semiconductor chip includes a second substrate, a second insulating layer on an upper surface of the second substrate contacting the first insulating layer, and a second pad exposed through the second insulating layer contacting the first pad. The first pad has an inclined side surface and a first width that increases toward the first substrate, and the second pad has an inclined side surface and a second width that increases toward the second substrate.
1 . A semiconductor package comprising:
a first semiconductor chip stacked on a second semiconductor chip;
the first semiconductor chip including a first substrate, a first insulating layer on a lower surface of the first substrate, and a first pad exposed through the first insulating layer,
wherein the first semiconductor chip further includes a first seed layer,
wherein an upper surface of the first pad contacts the first seed layer, and
wherein an inclined side surface of the first pad is surrounded by the first insulating layer; and
the second semiconductor chip including a second substrate, a second insulating layer on an upper surface of the second substrate contacting the first insulating layer, and a second pad exposed through the second insulating layer contacting the first pad,
wherein the first pad has a first width that increases toward the first substrate, and
the second pad has an inclined side surface and a second width that increases toward the second substrate.
2 . The semiconductor package of claim 1 , wherein an angle formed between the inclined side surface of the first pad and a lower surface of the first pad is in a range from about 90° to about 110°.
3 . The semiconductor package of claim 1 , wherein a width of the upper surface of the first pad in in a range from about 1.2 um to about 12 um, and
a width of a lower surface of the first pad is in a range from about 1 um to about 10 um.
4 . The semiconductor package of claim 1 , wherein a height of the first pad is in a range from about 0.5 um to about 2 um.
5 . The semiconductor package of claim 1 , wherein a width of a lower surface of the first pad is the same as a width of an upper surface of the second pad.
6 . The semiconductor package of claim 1 , wherein a width of a lower surface of the first pad is greater than a width of an upper surface of the second pad.
7 . The semiconductor package of claim 1 , wherein a width of a lower surface of the first pad is less than a width of an upper surface of the second pad.
8 . The semiconductor package of claim 1 , wherein:
the second semiconductor chip further includes a second seed layer contacting a lower surface of the second pad,
the first seed layer further includes a first extension portion extending from an end of the first seed layer and interposed between the inclined side surface of the first pad and the first insulating layer,
the second seed layer further includes a second extension portion extending from an end of the second seed layer and interposed between the inclined side surface of the second pad and the second insulating layer, and
the first extension portion and the second extension portion are in contact with each other.
9 . The semiconductor package of claim 1 , wherein a lower surface of the first seed layer is disposed at a same level as the upper surface of the first pad, and
a width of the upper surface of the first pad is the same as a width of the lower surface of the first seed layer.
10 . The semiconductor package of claim 1 , wherein the first seed layer has an inclined side surface and a width that increases toward the first substrate.
11 . The semiconductor package of claim 1 , wherein a lower surface of the first pad has a convex shape downward-facing toward the second substrate, and
an upper surface of the second pad has a convex shape upward-facing toward the first substrate.
12 . The semiconductor package of claim 11 , further comprising:
a groove in a second bonding portion outside a first bonding portion in which the lower surface of the first pad and the upper surface of the second pad contact each other,
wherein the first insulating layer and the second insulating layer contact each other in the groove.
13 . A semiconductor package comprising:
a first semiconductor chip stacked on a second semiconductor chip;
the first semiconductor chip including a first substrate, a first wiring structure under the first substrate, a first pad connected to the first wiring structure, and a first insulating layer surrounding the first pad,
wherein the first semiconductor chip further includes a connection pad surrounded by the first insulating layer, spaced apart from the first pad, having an inclined side surface, and having a width that increases toward the first substrate; and
the second semiconductor chip including a second substrate, a second wiring structure on the second substrate, a second pad connected to the second wiring structure and contacting the first pad, and a second insulating layer surrounding the second pad and contacting the first insulating layer,
wherein an angle formed between a side surface of the first pad and a lower surface of the first pad is in a range from about 90° to about 110°, and
an angle between a side surface of the second pad and an upper surface of the second pad is in a range from about 90° to about 110°.
14 . The semiconductor package of claim 13 , further comprising:
a redistribution structure electrically connected to the second semiconductor chip; and
a vertical connection structure connected between the connection pad and the redistribution structure.
15 . The semiconductor package of claim 13 , wherein each of the first pad and the second pad has a trapezoidal shape.
16 . A semiconductor package comprising:
a first semiconductor chip stacked on a second semiconductor chip;
the first semiconductor chip including a first substrate, a first pad under the first substrate, and a first insulating layer surrounding the first pad; and
the second semiconductor chip including a second substrate, a second pad on the second substrate, and a second insulating layer surrounding the second pad and contacting the first insulating layer,
wherein the first pad includes a lower surface and an opposing upper surface,
the second pad includes an upper surface contacting the lower surface of the first pad and an opposing lower surface,
a width of the upper surface of the first pad is greater than a width of the lower surface of the first pad,
a width of the lower surface of the second pad is greater than a width of the upper surface of the second pad, and
the width of the lower surface of the first pad is different from the width of the upper surface of the second pad.
17 . The semiconductor package of claim 16 , wherein an angle formed between a side surface of the first pad and a lower surface of the first insulating layer is in a range from about 70° to about 90°.
18 . The semiconductor package of claim 17 , wherein the first semiconductor chip further includes a first seed layer on the first pad, and
an angle formed between a side surface of the first pad and a lower surface of the first seed layer is in a range from about 70° to about 90°.