Semiconductor device, package structure and method of fabricating the same
A package structure includes a semiconductor die, a first insulating encapsulant, a plurality of first conductive features, an interconnect structure and bump structures. The semiconductor die includes a plurality of conductive pillars made of a first material. The first insulating encapsulant is encapsulating the semiconductor die. The first conductive features are disposed on the semiconductor die and electrically connected to the conductive pillars. The first conductive features include at least a second material different from the first material. The interconnect structure is disposed on the first conductive features, wherein the interconnect structure includes a plurality of connection structures made of the second material. The bump structures are electrically connecting the first conductive features to the connection structures, wherein the bump structures include a third material different from the first material and the second material.
1 . A method of fabricating a package structure, comprising:
forming a first insulating encapsulant encapsulating a plurality of semiconductor dies, wherein the plurality of semiconductor dies comprises a plurality of conductive pillars made of a first material;
forming a redistribution layer disposed on and electrically connected to the plurality of semiconductor dies, wherein the redistribution layer consists of a dielectric layer, first seed layers, second seed layers, and copper-free conductive features, and forming the redistribution layer comprises:
forming the dielectric layer on the first insulating encapsulant, and patterning the dielectric layer to form openings revealing the plurality of conductive pillars;
forming a seed layer in the openings of the dielectric layer, and patterning the seed layer to form the first seed layers and the second seed layers separated from one another, wherein the first seed layers are electrically connected to a first portion of the plurality of conductive pillars, and the second seed layers are electrically connected to a second portion of the plurality of conductive pillars, wherein the first seed layers and the second seed layers include titanium;
forming copper-free conductive features on the first seed layers and the second seed layers, wherein the forming of the copper-free conductive features comprises forming a plurality of first conductive features on the first seed layers, and forming a plurality of second conductive features on the second seed layers, wherein the plurality of first conductive features and the plurality of second conductive features respectively includes a nickel via portion and a nickel body portion, and a bottom surface and sidewalls of the nickel via portion is surrounded by the first seed layers or the second seed layers, and the nickel body portion is directly disposed on the nickel via portion, and sidewalls and a top surface of the nickel body portion are uncovered by the first seed layers and the second seed layers, and wherein the nickel via portion and the nickel body portion of the plurality of first conductive features are vertically aligned with the first portion of the plurality of conductive pillars along a build-up direction;
forming a plurality of through vias on the nickel body portion of the plurality of second conductive features, wherein the plurality of through vias is misaligned with the second portion of the plurality of conductive pillars along the build-up direction, and is made of the first material;
providing an interconnect structure over the plurality of first conductive features, wherein the interconnect structure comprises a plurality of connection structures made of nickel, wherein the plurality of through vias is surrounding the interconnect structure; and
providing bump structures in between the nickel body portion of the plurality of first conductive features and the plurality of connection structures, and performing a reflow process so that the bump structures are electrically joining the plurality of first conductive features to the plurality of connection structures, wherein the bump structures comprise a second material different from the first material and different from nickel.
2 . The method according to claim 1 , wherein after performing the reflow process,
a first intermetallic compound is formed between the plurality of first conductive features and the bump structures, wherein taking a sum of a thickness T1 of the first intermetallic compound and a thickness TB of the bump structures as 100%, the thickness T1 of the first intermetallic compound is in a range of 5% to 20%, and
a second intermetallic compound is formed between the plurality of connection structures and the bump structures, wherein taking a sum of a thickness T2 of the second intermetallic compound and the thickness TB of the bump structures as 100%, the thickness T2 of the second intermetallic compound is in a range of 5% to 20%.
3 . The method according to claim 1 , wherein the precious metal layer is a gold layer, and after performing a reflow process to join the bump structures to the plurality of first conductive features, the gold layer dissolves to form an Au-Sn based intermetallic compound between the plurality of first conductive features and the bump structures.
4 . The method according to claim 3 , wherein after performing the reflow process, the gold layer melts to form gold elements located in the bump structures.
5 . The method according to claim 1 , wherein the precious metal layer is formed over the plurality of second conductive features prior to forming the plurality of through vias, and the plurality of through vias is formed directly on the precious metal layer and over the plurality of second conductive features.
6 . The method according to claim 1 , further comprising forming a second insulating encapsulant disposed on the first insulating encapsulant and encapsulating the interconnection structure and the bump structures.
7 . The method according to claim 1 , wherein the nickel body portion of the plurality of second conductive features is formed to extend from a position over a top surface of the second portion of the plurality of conductive pillars towards a position beyond sidewalls of the plurality of semiconductor dies.
8 . A method, comprising:
forming first conductive features and second conductive features disposed on and electrically connected to a semiconductor die, wherein the first conductive features and the second conductive features are vertically overlapped with the semiconductor die and are made of nickel;
forming a first metallic layer on the first conductive features and forming a second metallic layer on the second conductive features, wherein the first metallic layer and the second metallic layer are vertically overlapped with the semiconductor die, and a bottom surface of the first metallic layer is horizontally aligned with a bottom surface of the second metallic layer, and a top surface of the first metallic layer is horizontally aligned with a top surface of the second metallic layer;
providing an interconnection die comprising through substrate vias, conductive pads disposed on the through substrate vias, and nickel-containing connection structures electrically connected to the conductive pads, wherein the through substrate vias, the conductive pads and the nickel-containing connection structures are vertically overlapped with one another;
after forming the nickel-containing connection structures on the interconnection die, bonding the interconnection die to the semiconductor die by joining the first conductive features to the nickel-containing connection structures through a plurality of bump structures, wherein the plurality of bump structures contains tin, and performing a reflow process to melt the first metallic layer so that a metallic element is formed in the plurality of bump structures, and wherein after the reflow process, a bottom surface of the plurality of bump structures is aligned with a bottom surface of the second metallic layer;
forming through vias directly on the second metallic layer, and over the second conductive features;
forming an underfill structure laterally surrounding and contacting the first conductive features, the nickel-containing connection structures of the interconnection die and the plurality of bump structures, wherein the underfill structure is vertically non-overlapped with the through substrate vias of the interconnection die; and
after forming the through vias, forming an insulating encapsulant covering and contacting a portion of the second metallic layer that is vertically overlapped with the semiconductor die, and wherein the insulating encapsulant is laterally surrounding the through vias.
9 . The method according to claim 8 , wherein joining the first conductive features to the nickel-containing connection structures through the plurality of bump structures comprises performing the reflow process to form a first intermetallic compound between the first conductive features and the plurality of bump structures, and to form a second intermetallic compound between the nickel-containing connection structures and the plurality of bump structures.
10 . The method according to claim 9 , wherein the first intermetallic compound comprises AuSn 4 and Ni 3 Sn 4 , and the second intermetallic compound includes Ni 3 Sn 4 .
11 . The method according to claim 9 , wherein taking a sum of a thickness T1 of the first intermetallic compound and a thickness TB of the bump structures as 100%, the first intermetallic compound is formed with the thickness T1 in a range of 5% to 20%, and taking a sum of a thickness T2 of the second intermetallic compound and the thickness TB of the bump structures as 100%, the second intermetallic compound is formed with the thickness T2 in a range of 5% to 20%.
12 . The method according to claim 8 , wherein the first metallic layer and the second metallic layer are made from a material selected from the group consisting of gold (Au), palladium (Pd) and platinum (Pt).
13 . The method according to claim 8 , wherein the metallic element formed in the plurality of bump structures include gold elements.
14 . The method according to claim 8 , wherein after forming the underfill structure, a top surface of the underfill structure is aligned with an interface between the nickel-containing connection structures and the conductive pads.
15 . A method, comprising:
forming first conductive features and second conductive features over a substrate, wherein the first conductive features and the second conductive features have aligned top surfaces;
forming a precious metal layer on the top surfaces of the first conductive features and the second conductive features;
providing an interconnection die, comprising a die substrate, through substrate vias embedded in the die substrate, and connection structures disposed on the through substrate vias; and
performing a reflow process to join a plurality of bump structures to the connection structures and the first conductive features, wherein during the reflow process, the plurality of bump structures and the precious metal layer are sandwiched between two nickel-containing interfaces of the connection structures and the first conductive features, and after the reflow process, a first intermetallic compound consisting of AuSn 4 and Ni 3 Sn 4 is formed between the first conductive features and the plurality of bump structures, a second intermetallic compound consisting of Ni 3 Sn 4 is formed between the connection structures and the plurality of bump structures, and the plurality of bump structures have a greater thickness than the first intermetallic compound and the second intermetallic compound, the precious metal layer on the first conductive features is melted during the reflow process and dissolved into the plurality of bump structures so that metal elements originating from the precious metal layer are located in the plurality of bump structures and physically separated from the first intermetallic compound and the second intermetallic compound, while the precious metal layer is retained on the second conductive features, and the metal elements are vertically overlapped with the through substrate vias of the interconnection die;
forming through vias on the precious metal layer over the second conductive features;
forming an insulating encapsulant surrounding the interconnection die and the through vias; and
performing a thinning step to remove portions of the insulating encapsulant to reveal a top surface of the through vias and a top surface of the through substrate vias of the interconnection die, wherein the top surface of the through vias, the top surface of the through substrate vias and a top surface of the insulating encapsulant are coplanar and levelled with one another after the thinning step.
16 . The method according to claim 15 , wherein the precious metal layer comprises gold (Au), palladium (Pd) or platinum (Pt).
17 . The method according to claim 15 , further comprising:
forming an underfill structure surrounding the first conductive features, the connection structure and the plurality of bump structures, and
forming the insulating encapsulant to surround the underfill structure.
18 . The method according to claim 15 , further comprises forming a redistribution layer on the insulating encapsulant, wherein the redistribution layer is electrically connected to the through vias and the through substrate vias of the interconnection die.
19 . The method according to claim 15 , wherein prior to forming the first conductive features and the second conductive features, the method further comprises:
placing a first semiconductor die and a second semiconductor die over the substrate, wherein the first semiconductor die and the second semiconductor die comprises a plurality of conductive pillars;
forming the first conductive features and the second conductive features on the plurality of conductive pillars of the first semiconductor die and the second semiconductor die, and over the substrate, and
wherein after performing the reflow process, the metal elements are further vertically overlapped with a portion of plurality of conductive pillars of the first semiconductor die and the second semiconductor die, and the precious metal layer retained on the second conductive features is vertically overlapped with another portion of plurality of conductive pillars of the first semiconductor die and the second semiconductor die.
20 . The method according to claim 15 , wherein after the thinning step to reveal the top surface of the through vias and the top surface of the through substrate vias, a redistribution layer is formed on the interconnection die and the insulating encapsulant, wherein forming the redistribution layer comprises:
forming first conductive via portions electrically connected to the top surface of the through vias and the top surface of the through substrate vias, and forming a first dielectric layer laterally surrounding the first conductive via portions, and a height of the first dielectric layer is equal to a height of the first conductive via portions;
forming conductive elements disposed on and electrically connected to the first conductive via portions; and
forming second conductive via portions disposed on and electrically connected to the conductive elements, and forming a second dielectric layer disposed on the first dielectric layer, and laterally surrounding the conductive elements and the second conductive via portions.