IP Library Granted Patent US 12708013
Granted Patent B2
US 12708013 · App. 17/711,749 · Granted Aug 11, 2026

Substrate with low-permittivity core and buildup layers

Inventors: Brandon Christian Marin (Gilbert, AZ); Hamid R. Azimi (Paradise Valley, AZ); Sri Chaitra Jyotsna Chavali (Gilbert, AZ); Tarek A. Ibrahim (Mesa, AZ); Wei-Lun K Jen (Phoenix, AZ); Rahul Manepalli (Chandler, AZ); Kevin T. McCarthy (Tempe, AZ)
Assignee: Intel Corporation
H10W70/69H10W70/635H10W70/685
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Quick Facts
Patent No.
US 12708013
App. No.
17/711,749
Granted
Aug 11, 2026
Kind
B2
Abstract

In one embodiment, a package substrate includes a substrate core, buildup layers, and one or more conductive traces. The substrate core includes at least one dielectric layer with hollow glass fibers. The buildup layers include dielectric layers below and above the substrate core.

Claims (40)

1 . A package substrate, comprising:

a substrate core comprising one or more first dielectric layers, wherein the one or more first dielectric layers comprise hollow glass fibers;

a plurality of second dielectric layers, wherein the plurality of second dielectric layers are below and above the substrate core; and

one or more conductive traces through the package substrate.

2 . The package substrate of claim 1 , wherein the one or more first dielectric layers further comprise hollow glass cloth, wherein the hollow glass cloth comprises the hollow glass fibers.

3 . The package substrate of claim 2 , wherein the hollow glass cloth has a thermoplastic coating.

4 . The package substrate of claim 1 , wherein the one or more first dielectric layers further comprise hollow pockets.

5 . The package substrate of claim 4 , wherein the one or more first dielectric layers further comprise hollow filler particles, wherein the hollow pockets are within the hollow filler particles.

6 . The package substrate of claim 5 , wherein the hollow filler particles comprise hollow silica filler.

7 . The package substrate of claim 4 , wherein the one or more first dielectric layers further comprise cage polymers, wherein the hollow pockets are within the cage polymers.

8 . The package substrate of claim 7 , wherein the cage polymers comprise silesquioxane polymers, phenylsilsequioxane polymers, or polycaprolactone polymers.

9 . The package substrate of claim 1 , wherein the substrate core further comprises a plurality of copper foils, wherein the one or more first dielectric layers are between the plurality of copper foils.

10 . The package substrate of claim 1 , wherein the plurality of second dielectric layers comprises at least one layer with hollow glass fibers or hollow pockets.

11 . The package substrate of claim 1 , wherein one or more conductive traces comprise:

one or more through hole vias; and

one or more conductive contacts on a surface of the package substrate.

12 . The package substrate of claim 11 , wherein an integrated circuit die is coupled to the one or more conductive contacts on the surface of the package substrate.

13 . The package substrate of claim 1 , wherein the hollow glass fibers are configured to reduce a dielectric constant of the substrate core relative to a substrate core comprising solid glass fibers.

14 . The package substrate of claim 1 , wherein the hollow glass fibers are coated with resin.

15 . An integrated circuit package, comprising:

a package substrate, comprising:

a substrate core, wherein the substrate core comprises hollow glass cloth within a first dielectric material;

a plurality of buildup layers below and above the substrate core, wherein the plurality of buildup layers comprise a second dielectric material; and

one or more conductive traces through the package substrate, wherein the one or more conductive traces comprise one or more conductive contacts on a surface of the package substrate; and

one or more integrated circuit dies coupled to the one or more conductive contacts on the surface of the package substrate.

16 . The integrated circuit package of claim 15 , wherein the substrate core further comprises a plurality of copper foils, wherein the first dielectric material is between the plurality of copper foils.

17 . The integrated circuit package of claim 15 , wherein the substrate core further comprises hollow pockets within the first dielectric material, wherein the hollow pockets comprise hollow silica filler or cage polymers.

18 . The integrated circuit package of claim 17 , wherein the cage polymers comprise silesquioxane polymers, phenylsilsequioxane polymers, or polycaprolactone polymers.

19 . The integrated circuit package of claim 15 , wherein the plurality of buildup layers comprises at least one layer with hollow glass cloth or hollow pockets.

20 . The integrated circuit package of claim 15 , wherein the one or more integrated circuit dies comprise processing circuitry, memory circuitry, or communication circuitry.

21 . An electronic device, comprising:

a printed circuit board; and

an integrated circuit package coupled to the printed circuit board, wherein the integrated circuit package comprises:

a package substrate, comprising:

a substrate core, wherein the substrate core comprises hollow glass cloth within a first dielectric material;

a plurality of buildup layers below and above the substrate core, wherein the plurality of buildup layers comprise a second dielectric material; and

one or more conductive traces through the package substrate; and

one or more integrated circuit dies coupled to the package substrate.

22 . The electronic device of claim 21 , wherein the one or more integrated circuit dies comprise processing circuitry, memory circuitry, or communication circuitry.

23 . The electronic device of claim 21 , wherein the substrate core further comprises hollow pockets within the first dielectric material, wherein the hollow pockets comprise hollow silica filler or cage polymers.