IP Library Granted Patent US 12708018
Granted Patent B2
US 12708018 · App. 18/342,911 · Granted Aug 11, 2026

Method of manufacturing semiconductor device

Inventor: Takashi Saito (Matsumoto-city, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H10W72/073H10W72/07331
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Quick Facts
Patent No.
US 12708018
App. No.
18/342,911
Granted
Aug 11, 2026
Kind
B2
Abstract

A method of manufacturing a semiconductor module includes: placing, on a lower hot plate, an insulating wiring substrate having an electrically-conductive pattern formed on an insulating substrate; placing sintered materials on the electrically-conductive pattern; placing semiconductor chips on the sintered materials; placing a cushioning material over the semiconductor chips; placing an upper hot plate on the cushioning material; and sintering the sintered materials by pressurizing and heating the sintered materials via the cushioning material and the electronic components by the upper hot plate in a state where a space is provided between the upper hot plate and a part of the insulating substrate.

Claims (25)

1 . A method of manufacturing a semiconductor module comprising:

placing, on a lower hot plate, an insulating wiring substrate having an electrically-conductive pattern formed on an insulating substrate;

placing sinterable materials on the electrically-conductive pattern;

placing electronic components on the sinterable materials;

placing a cushioning material over the electronic components;

placing an upper hot plate on the cushioning material;

pressing the upper hot plate and the lower hot plate together so as to press the cushioning material, the electronic components, the sinterable materials, and the insulating wiring substrate together such that at least a portion of the cushioning material that corresponds to the electronic components becomes compressed and so as to form a space between the upper hot plate and the insulating substrate; and

with the upper hot plate and the lower hot plate pressed together, heating, by the upper hot plate, the sinterable materials via the cushioning material and the electronic components such that gas released from the sinterable materials is dischargeable through the space and the sinterable materials become sintered to join the electronic components to the electrically-conductive pattern of the insulating wiring substrate.

2 . The method of manufacturing the semiconductor module according to claim 1 , wherein the sinterable materials are pressurized by the upper hot plate such that an amount of change in a thickness of the at least a portion of the cushioning material before and after the pressing is smaller than a distance from the insulating substrate to surfaces, on a cushioning material side, of the electronic components.

3 . The method of manufacturing the semiconductor module according to claim 1 , wherein the cushioning material is a single cushioning material, and the placing includes placing the single cushioning material over the electronic components such that the single cushioning material is brought into contact with respective surfaces, on an upper hot plate side, of the electrically-conductive pattern, the sinterable materials, and the electronic components.

4 . The method of manufacturing the semiconductor module according to claim 3 , wherein the space is provided between another portion of the cushioning material and the insulating substrate.

5 . The method of manufacturing the semiconductor module according to claim 3 , wherein the pressing includes making no contact between the cushioning material and the insulating substrate.

6 . The method of manufacturing the semiconductor module according to claim 4 , wherein the pressing includes making no contact between the cushioning material and the insulating substrate.

7 . The method of manufacturing the semiconductor module according to claim 1 , wherein:

the electrically-conductive pattern includes a plurality of electrically-conductive patterns formed on the insulating substrate;

the sinterable materials are placed on each of at least two of the plurality of electrically-conductive patterns;

the electronic components are placed on the sinterable materials; and

the cushioning material includes a plurality of cushioning materials and cushioning materials from among the plurality of cushioning materials are individually placed on a set from among a plurality of sets, each set from among the plurality of sets including sinterable materials placed on a same electrically-conductive pattern from among the plurality of electrically-conductive patterns and electronic components placed on the sinterable materials.

8 . The method of manufacturing the semiconductor module according to claim 7 , wherein the plurality of cushioning materials further includes a cushioning material having a different thickness from other cushioning materials from among the plurality of cushioning materials, and the cushioning material having a different thickness is placed on at least one electrically-conductive pattern from among the plurality of electrically-conductive patterns on which no set is placed.

9 . The method of manufacturing the semiconductor module according to claim 1 , wherein the electronic components are semiconductor chips.

10 . The method of manufacturing the semiconductor module according to claim 1 , wherein the heating further includes heating, by the lower hot plate, the sinterable materials via insulating wiring substrate such that the sinterable materials release the gas so as to be discharged through the space and the sinterable materials becomes sintered thereby joining the electronic components to the electrically-conductive pattern by the sinterable materials being sintered.

11 . The method of manufacturing the semiconductor module according to claim 10 , wherein the heating, by the lower hot plate and the heating, by the upper hot plate, is simultaneous.

12 . The method of manufacturing the semiconductor module according to claim 1 , wherein the at least a portion of the cushioning material is a first portion of the cushioning material that corresponds to the electronic components that becomes compressed, and

a second portion of the cushioning material that does not correspond to the electronic components is not compressed and is spaced apart from the insulating substrate so as to form a space between the second portion of the cushioning material and the insulating substrate.

13 . The method of manufacturing the semiconductor module according to claim 1 , wherein the cushioning material is constituted by a carbon sheet.