IP Library Granted Patent US 12708021
Granted Patent B2
US 12708021 · App. 18/597,094 · Granted Aug 11, 2026

Semiconductor structure and manufacturing method thereof

Inventors: Manikandan Arumugam (Tainan, TW); Tsung-Yi Yang (Tainan City, TW); Chien-Chih Chen (Tainan, TW); Mu-Han Cheng (Tainan, TW); Kuo-Hsien Cheng (Tainan City, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H10W72/90H10W72/019H10W99/00H10W72/01938H10W72/01953H10W72/923H10W72/9415H10W72/952H10W72/953H10W80/312H10W80/327H10W90/792
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12708021
App. No.
18/597,094
Granted
Aug 11, 2026
Kind
B2
Abstract

Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first conductive structure disposed within a first layer of the semiconductor structure. The semiconductor structure includes a dielectric structure disposed within a second layer of the semiconductor structure, with the second layer being disposed on the first layer. The semiconductor structure includes a second conductive structure disposed within a recessed portion of the dielectric structure that extends to the first conductive structure, with the second conductive structure having a concave recessed portion on a top surface of the second conductive structure. The semiconductor structure includes multiple layers of conductive material disposed within the concave recessed portion of the second conductive structure.

Claims (77)

1 . A semiconductor structure, comprising:

a first conductive structure disposed within a first layer of the semiconductor structure;

a dielectric structure disposed within a second layer of the semiconductor structure, the second layer being disposed on the first layer;

a second conductive structure disposed within a recessed portion of the dielectric structure that extends to the first conductive structure, the second conductive structure having a surface that forms a concave recessed portion in the second conductive structure; and

multiple layers of conductive material disposed within the concave recessed portion of the second conductive structure,

wherein the multiple layers of conductive material have at least one surface that is generally planar, and

wherein the multiple layers of conductive material comprise one or more of:

a conductive 2-dimensional (2D) layered material, or

a metal nitride material.

2 . The semiconductor structure of claim 1 ,

wherein the second conductive structure comprises copper.

3 . The semiconductor structure of claim 1 ,

wherein the second conductive structure comprises a 2D layered material.

4 . The semiconductor structure of claim 1 ,

wherein the multiple layers of conductive material comprise a carbon-based material.

5 . The semiconductor structure of claim 1 , wherein the conductive 2D layered material comprises:

a heterostructure conductive of different conductive 2D layered materials or differently doped 2D materials, or

a single conductive 2D material.

6 . The semiconductor structure of claim 1 ,

wherein the at least one surface of the multiple layers of conductive material is generally planar with a surface of the dielectric structure.

7 . The semiconductor structure of claim 1 ,

wherein the dielectric structure comprises:

a bonding dielectric layer including one or more recessed portions; and

silicon oxynitride material within the one or more recessed portions of the bonding dielectric layer.

8 . The semiconductor structure of claim 7 ,

wherein the bonding dielectric layer includes silicon oxynitride, silicon dioxide, silicon oxycarbide, silicon carbon nitride, or a hybrid dielectric.

9 . The semiconductor structure of claim 7 ,

wherein the one or more recessed portions of the bonding dielectric layer comprise voids extending into the bonding dielectric layer, the voids having a thickness less than approximately 20 nanometers.

10 . The semiconductor structure of claim 7 ,

wherein the bonding dielectric layer comprises a silicon dioxide material disposed within the one or more recessed portions of the bonding dielectric layer.

11 . The semiconductor structure of claim 1 ,

wherein a first wafer of the semiconductor structure comprises the first conductive structure, the dielectric structure, the second conductive structure, and the multiple layers of conductive material, and

wherein a second wafer comprises, at a surface of the second wafer,

an additional dielectric structure bonded to the dielectric structure of the first wafer; and

a third conductive structure bonded to the multiple layers of conductive material of the first wafer.

12 . The semiconductor structure of claim 11 ,

wherein the third conductive structure of the second wafer comprises one or more of:

the conductive 2D layered material,

a heterostructure conductive 2D layered material, or

the metal nitride material.

13 . A semiconductor structure, comprising:

a first wafer comprising:

a first semiconductor substrate;

a first conductive structure in the first semiconductor substrate;

a first dielectric structure, residing on the first semiconductor substrate, that includes a first recessed portion;

a second conductive structure disposed within the first recessed portion, the second conductive structure having a surface that forms a first concave recessed portion in the second conductive structure; and

a first conductive material disposed within the first concave recessed portion of the second conductive structure,

wherein the first conductive material has at least one surface that is generally planar; and

a second wafer comprising:

a second semiconductor substrate,

a third conductive structure in the second semiconductor substrate,

wherein, in a sideview of the semiconductor structure, the third conductive structure is offset from the first conductive structure;

a second dielectric structure, residing on the second semiconductor substrate, that includes a second recessed portion;

a fourth conductive structure disposed within the second recessed portion, the fourth conductive structure having a surface that forms a second concave recessed portion in the fourth conductive structure; and

a second conductive material disposed within the second concave recessed portion,

wherein the second conductive material has at least one surface that is generally planar,

wherein the fourth conductive structure is laterally offset relative to the second conductive structure.

14 . The semiconductor structure of claim 13 ,

wherein the second dielectric structure is bonded to the first dielectric structure, and the second conductive material is bonded to the first conductive material.

15 . The semiconductor structure of claim 13 ,

wherein one or more of the second conductive structure or the fourth conductive structure comprises copper or a 2-dimensional (2D) layered material.

16 . The semiconductor structure of claim 13 ,

wherein one or more of the first conductive material or the second conductive material comprises multiple layers of conductive material.

17 . A method of forming a semiconductor structure, comprising:

depositing a conductive structure within a recessed portion of a dielectric structure;

polishing a top surface of the semiconductor structure, the polishing forming a concave recessed portion in the conductive structure; and

forming a conductive material within the concave recessed portion to form a substantially planar top surface for the semiconductor structure, wherein forming the conductive material comprises depositing multiple two-dimensional layers of the conductive material within the concave recessed portion.

18 . The method of claim 17 ,

wherein forming the conductive material within the concave recessed portion comprises:

forming multiple layers of the conductive material within the concave recessed portion.

19 . The method of claim 17 ,

wherein the method further comprises:

forming an additional dielectric structure and an additional conductive material;

bonding the conductive material to the additional conductive material; and

bonding the dielectric structure to the additional dielectric structure.

20 . The method of claim 19 ,

wherein the additional conductive material comprises multiple layers of the additional conductive material.