Package structure and method of manufacturing the same
A package structure includes a semiconductor die, a redistribution circuit structure, and conductive pads. The redistribution circuit structure is located on and electrically connected to the semiconductor die, the redistribution circuit structure includes a first contact pad having a first width and a second contact pad having a second width. The conductive pads are located on and electrically connected to the redistribution circuit structure through connecting to the first contact pad and the second contact pad, the redistribution circuit structure is located between the conductive pads and the semiconductor die. The first width of the first contact pad is less than a width of the conductive pads, and the second width of the second contact pad is substantially equal to or greater than the width of the conductive pads.
1 . A package structure, comprising:
a plurality of semiconductor dies; and
a first redistribution circuit structure, disposed over the plurality of semiconductor dies, the first redistribution circuit structure comprising a first contact pad having a first width and a second contact pad having a second width, and the first width being less than the second width, wherein the first contact pad and the second contact pad are comprised in an outermost metallization layer of the first redistribution circuit structure away from the plurality of semiconductor dies;
wherein in a cross section of the package structure along a stacking direction of the plurality of semiconductor dies and the first redistribution circuit structure, the first contact pad is aside of the plurality of semiconductor dies, and the second contact pad is overlapped with the plurality of semiconductor dies.
2 . The package structure of claim 1 , wherein the first contact pad and the second contact pad are comprised in a topmost metallization layer of the first redistribution circuit structure.
3 . The package structure of claim 1 , wherein the first contact pad is surrounded by a buffer region, and at least 50% of an overall area of the buffer region is occupied by a metal feature comprised in the topmost metallization layer.
4 . The package structure of claim 1 , further comprises:
a second redistribution circuit structure, disposed over the plurality of semiconductor dies, the plurality of semiconductor dies being between the first redistribution circuit structure and the second redistribution circuit structure; and
a plurality of conductive pillars, next to the plurality of semiconductor dies and connecting the first redistribution circuit structure and the second redistribution circuit structure.
5 . The package structure of claim 4 , further comprises:
an insulating encapsulation, laterally encapsulating the plurality of semiconductor dies and the plurality of conductive pillars, wherein the plurality of conductive pillars penetrate through the insulating encapsulation.
6 . The package structure of claim 5 , wherein in the cross section the first contact pad and the second contact pad are overlapped with the insulating encapsulation and the conductive pillars.
7 . The package structure of claim 4 , further comprising at least one of:
a plurality of first connectors, disposed over the first redistribution circuit structure, wherein the first redistribution circuit structure is between the plurality of first connectors and the plurality of semiconductor dies; or
a plurality of second connectors, disposed over the second redistribution circuit structure, wherein the second redistribution circuit structure is between the plurality of second connectors and the plurality of semiconductor dies.
8 . The package structure of claim 1 , further comprises:
an insulating encapsulation, laterally encapsulating the plurality of semiconductor dies and over the first redistribution circuit structure; and
a plurality of connectors, disposed over the first redistribution circuit structure, wherein the first redistribution circuit structure is between the plurality of connectors and the insulating encapsulation.
9 . The package structure of claim 8 , wherein in the cross section, the first contact pad and the second contact pad are overlapped with the insulating encapsulation.
10 . The package structure of claim 1 , further comprising:
a heat dissipating element, disposed over the plurality of semiconductor dies, wherein the plurality of semiconductor dies are disposed between the heat dissipating element and the first redistribution circuit structure.
11 . The package structure of claim 1 , further comprising:
a warpage-controlling carrier, disposed over the plurality of semiconductor dies, wherein the plurality of semiconductor dies are disposed between the warpage-controlling carrier and the first redistribution circuit structure.
12 . A package structure, comprising:
a redistribution circuit structure, comprising a plurality of first contact pads having a first width and a plurality of second contact pads having a second width, and the first width being less than the second width;
a semiconductor die, disposed over the redistribution circuit structure within a device region of the package structure;
a plurality of first conductive pads standing on the plurality of first contact pads and having a third width greater than the first width, wherein the plurality of first contact pads are between the semiconductor die and the plurality of first conductive pads, and at least one of the plurality of first conductive pads is in direct contact with a respective one of the plurality of first contact pads; and
a plurality of second conductive pads standing on the plurality of second contact pads and having a fourth width less than or substantially equal to the second width, wherein the plurality of second contact pads are between the semiconductor die and the plurality of second conductive pads.
13 . The package structure of claim 12 , further comprising:
an insulating encapsulation, over the redistribution circuit structure within a peripheral region of the package structure, the insulating encapsulating embedding the semiconductor die, and the peripheral region enclosing the device region; and
a plurality of conductive terminals, standing on the plurality of first conductive pads and the plurality of second conductor pads,
wherein the plurality of first contact pads and the plurality of second contact pads are comprised in an outermost metallization layer of the redistribution circuit structure away from the semiconductor die.
14 . The package structure of claim 13 , wherein the package structure further has a dummy region overlapped with the device region and the peripheral region,
wherein the dummy region is disposed at a first corner of the device region, and a second corner of the dummy region is disposed in the peripheral region and is disposed on a diagonal line of the device region passing through the first corner of the device region.
15 . The package structure of claim 14 , wherein the dummy region and the device region is free of the plurality of first contact pads.
16 . The package structure of claim 12 , wherein the plurality of first contact pads each are separated from the plurality of second contact pads and are further surrounded by a buffer region, and at least 50% of an overall area of the buffer region is occupied by a metal feature formed in a same layer where the plurality of first contact pads and the plurality of second contact pads formed therein.
17 . A package structure, comprising:
a back-side redistribution structure;
a plurality of semiconductor dies, standing over the back-side redistribution structure;
a plurality of conductive pillars, standing over the back-side redistribution structure next to the plurality of semiconductor dies;
an insulating encapsulation, covering the plurality of semiconductor dies and the plurality of conductive pillars;
a front-side redistribution structure, disposed over the insulating encapsulation, the insulating encapsulation interposed between the back-side redistribution structure and the front-side redistribution structure, wherein the front-side redistribution structure comprises a plurality of first contact pads having a first width and a plurality of second contact pads having a second width, and the first width is less than the second width, wherein in a cross-section along a stacking direction of the back-side redistribution structure and the front-side redistribution structure, the plurality of first contact pads are overlapped with the insulating encapsulation and offset from the plurality of semiconductor dies; and
a plurality of terminals, disposed over the front-side redistribution structure, the front-side redistribution structure being between the plurality of terminals and the insulating encapsulation.
18 . The package structure of claim 17 , wherein in the cross-section along the stacking direction, the plurality of second contact pads are overlapped with the insulating encapsulation and the plurality of semiconductor dies.
19 . The package structure of claim 17 , further comprising one of:
a heat dissipating element, disposed over the semiconductor die, wherein the semiconductor die is disposed between the heat dissipating element and the first redistribution circuit structure, or
a warpage-controlling carrier, disposed over the semiconductor die, wherein the semiconductor die is disposed between the warpage-controlling carrier and the first redistribution circuit structure.
20 . The package structure of claim 17 , further comprising:
a plurality of additional terminals, disposed over the back-side redistribution structure, the back-side redistribution structure being between the plurality of additional terminals and the insulating encapsulation.