Multilayer encapsulation for humidity robustness and highly accelerated stress tests and related fabrication methods
A semiconductor die includes a semiconductor body, and a multi-layer environmental barrier on the semiconductor body. The multi-layer environmental barrier includes a plurality of sublayers that are stacked on the semiconductor body. Each of the sublayers comprises a respective stress in one or more directions, where the respective stresses of at least two of the sublayers are different. The sublayers may include a first stressor sublayer comprising first stress, and a second stressor sublayer comprising a second stress that at least partially compensates for the first stress in the one or more directions. Related devices and methods of fabrication are also discussed.
1 . A semiconductor die, comprising:
a semiconductor body; and
a multi-layer environmental barrier comprising a plurality of sublayers that are stacked on the semiconductor body,
wherein each of the sublayers comprises a respective stress in one or more directions, and wherein the respective stresses of at least two of the sublayers oppose one another, and
wherein the at least two of the sublayers comprise a first stressor sublayer of a first material and a second stressor sublayer of a second material, wherein the first material has a greater density than the second material, and the first stressor sublayer is thicker than the second stressor sublayer.
2 . The semiconductor die of claim 1 , wherein the first stressor sublayer is configured to provide a first stress, and the second stressor sublayer is configured to provide a second stress that at least partially compensates for the first stress in the one or more directions.
3 . The semiconductor die of claim 2 , wherein the first stress is tensile, and the second stress is compressive.
4 . The semiconductor die of claim 2 , wherein the first and second stressor sublayers comprise first and second oxide materials, respectively, wherein the first oxide material is different than the second oxide material.
5 . The semiconductor die of claim 2 , wherein at least one of the first or second stressor sublayers comprises a metal insulating material.
6 . The semiconductor die of claim 5 , wherein at least one of the sublayers comprises a conductive metal layer.
7 . The semiconductor die of claim 5 , wherein the metal insulating material comprises at least one of aluminum oxide, zirconium oxide, or hafnium oxide.
8 . The semiconductor die of claim 5 , wherein another of the first or second stressor sublayers comprises a non-metal insulating material.
9 . The semiconductor die of claim 8 , wherein the metal insulating material comprises aluminum oxide, and wherein the non-metal insulating material comprises silicon oxide.
10 . The semiconductor die of claim 2 , wherein the sublayers comprise a repeating layer structure that includes the first and second stressor sublayers.
11 . The semiconductor die of claim 10 , wherein the repeating layer structure comprises:
a binary structure in which the first and second stressor sublayers are stacked;
a ternary structure in which the first stressor sublayer, the second stressor sublayer, and a third stressor sublayer are stacked; and/or
a quaternary structure in which the first stressor sublayer, the second stressor sublayer, the third stressor sublayer, and a fourth stressor sublayer are stacked.
12 . The semiconductor die of claim 11 , wherein the multi-layer environmental barrier comprises at least two of the repeating layer structure, at least ten of the repeating layer structure, or at least twenty of the repeating layer structure.
13 . The semiconductor die of claim 2 , wherein the first stressor sublayer is between the second stressor sublayer and the semiconductor body.
14 . The semiconductor die of claim 2 , wherein a density of at least one of a first material of the first stressor sublayer or a second material of the second stressor sublayer is greater than silicon nitride.
15 . The semiconductor die of claim 2 , wherein a ratio of a thickness of the first stressor sublayer to a thickness of the second stressor sublayer is about 2:1 or more, about 5:1 or more, or about 8:1 or more.
16 . The semiconductor die of claim 2 , further comprising:
a gate, a source contact, and a drain contact on the semiconductor body,
wherein the first and second stressor sublayers conformally extend directly on the gate, the source contact, and the drain contact with respective thicknesses that are substantially uniform.
17 . The semiconductor die of claim 2 , wherein the first and second stressor sublayers comprise Atomic Layer Deposition (ALD) layers.
18 . The semiconductor die of claim 1 , wherein the multi-layer environmental barrier comprises one or more diffusion barrier properties, and wherein a collective stress of the sublayers of the multi-layer environmental barrier is less than that of one or more silicon nitride layers comprising at least one of the diffusion barrier properties.
19 . The semiconductor die of claim 18 , wherein a total thickness of the multi-layer environmental barrier is about 500 Angstroms to about 3500 Angstroms.
20 . A semiconductor die comprising:
a semiconductor body;
a multi-layer environmental barrier comprising two or more sublayers that are stacked on the semiconductor body in a repeating layer structure; and
one or more silicon nitride layers between the semiconductor body and the multi-layer environmental barrier,
wherein the multi-layer environmental barrier comprises two or more diffusion barrier properties, wherein a collective stress of the multi-layer environmental barrier is less than that of the one or more silicon nitride layers comprising at least one of the diffusion barrier properties, and wherein a thickness of the multi-layer environmental barrier is less than a thickness of the one or more silicon nitride layers.
21 . The semiconductor die of claim 20 , wherein each of the sublayers is configured to provide a respective stress in one or more directions, and wherein the respective stresses of at least two of the sublayers oppose one another and at least partially compensate for the respective stress of one of the sublayers directly thereabove or directly therebelow.
22 . The semiconductor die of claim 21 , wherein the at least two of the sublayers comprise a first stressor sublayer configured to provide a first stress, and a second stressor sublayer configured to provide a second stress that at least partially compensates for the first stress in the one or more directions.
23 . The semiconductor die of claim 22 , wherein the first stress at least partially compensates for a third stress of the one or more silicon nitride layers directly thereon, and wherein the collective stress of the multi-layer environmental barrier is less than the third stress of the one or more silicon nitride layers over an operating temperature range of a packaged device including the semiconductor die.
24 . The semiconductor die of claim 22 , wherein at least one of the first or second stressor sublayers comprises metal insulating material.
25 . The semiconductor die of claim 24 , wherein another of the first or second stressor sublayers comprises a metal.
26 . The semiconductor die of claim 24 , wherein the metal insulating material comprises at least one of aluminum oxide, zirconium oxide, or hafnium oxide.
27 . The semiconductor die of claim 24 , wherein another of the first or second stressor sublayers comprises a non-metal insulating material.
28 . A method of fabricating a semiconductor die, the method comprising:
providing a semiconductor body; and
forming a multi-layer environmental barrier comprising a plurality of sublayers that are stacked on the semiconductor body, wherein forming the multi-layer environmental barrier comprises:
forming a first stressor sublayer comprising a first stress; and
forming a second stressor sublayer comprising a second stress on the first stressor sublayer, wherein the second stress and the first stress oppose one another,
wherein the first stressor sublayer comprises a first material having a greater density than a second material of the second stressor sublayer, and the first stressor sublayer is thicker than the second stressor sublayer.
29 . The method of claim 28 , wherein the first stress is tensile, and the second stress is compressive.
30 . The method of claim 28 , wherein forming the multi-layer environmental barrier comprises forming the first and second stressor sublayers using Atomic Layer Deposition (ALD).
31 . The method of claim 30 , wherein forming the multi-layer environmental barrier comprises:
alternatingly performing a first ALD process to form the first stressor sublayer and a second ALD process to form the second stressor sublayer in a repeating layer structure.
32 . The method of claim 28 , wherein the first stressor sublayer comprises a first material having a greater density than a second material of the second stressor sublayer.
33 . The method of claim 28 , wherein the first and second stressor sublayers comprise first and second oxide materials, respectively, wherein the first oxide material is different than the second oxide material.
34 . The method of claim 28 , wherein at least one of the first or second stressor sublayers comprises a metal insulating material.
35 . The method of claim 34 , wherein another of the first or second stressor sublayers comprises a metal.
36 . The method of claim 34 , wherein the metal insulating material comprises at least one of aluminum oxide, zirconium oxide, or hafnium oxide.
37 . The method of claim 34 , wherein another of the first or second stressor sublayers comprises a non-metal insulating material.
38 . The method of claim 37 , wherein the metal insulating material comprises aluminum oxide, and wherein the non-metal insulating material comprises silicon oxide.
39 . A semiconductor die, comprising:
a semiconductor body; and
a multi-layer environmental barrier on the semiconductor body, the multi-layer environmental barrier comprising a first sublayer of a metal insulating material and a second sublayer of a non-metal insulating material that are stacked, wherein respective stresses of the first and second sublayers oppose one another,
wherein the first sublayer of the metal insulating material is thicker than the second sublayer of the non-metal insulating material.
40 . The semiconductor die of claim 39 , wherein the metal insulating material comprises a metal oxide or metal nitride, and wherein the non-metal insulating material comprises a non-metal oxide or a non-metal nitride.
41 . The semiconductor die of claim 39 , wherein the metal insulating material comprises at least one of aluminum (Al), zirconium (Zr), or hafnium (Hf), and wherein the non-metal insulating material comprises at least one of bismuth (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), or tellurium (Te).
42 . The semiconductor die of claim 39 , wherein the first sublayer is between the second sublayer and the semiconductor body.
43 . The semiconductor die of claim 39 , wherein the first sublayer comprises a first stress between particles of the metal insulating material, and the second sublayer comprises a second stress between particles of the non-metal insulating material that at least partially compensates for the first stress in one or more directions.