Method of filling gaps between dies using silicon dioxide

1 . A method of forming an integrated circuit structure, the method comprising:

bonding a first die to a first side of a semiconductor substrate;

bonding a second die to the first side of the semiconductor substrate, the second die being adjacent to the first die and a gap being defined between the first die and second die;

forming a first dielectric layer over the first and second dies and in the gap;

forming a first opening in the first dielectric layer in the gap; and

forming a second dielectric layer over the first dielectric layer and in the first opening, wherein the first dielectric layer comprises a higher film stress in absolute value than the second dielectric layer.

2 . The method of claim 1 , further comprising:

forming a second opening in the second dielectric layer over the first opening;

forming a third dielectric layer over the second dielectric layer and in the second opening;

forming a third opening in the third dielectric layer over the second opening;

forming a fourth dielectric layer over the third dielectric layer and in the third opening; and

forming a fourth opening in the fourth dielectric layer over the third opening, wherein the first dielectric layer comprises a higher film stress in absolute value than the second, third, and fourth dielectric layers.

3 . The method of claim 2 , wherein the first dielectric layer is made of a same material as the second, third, and fourth dielectric layers.

4 . The method of claim 2 , wherein the first dielectric layer is thicker than each of the second, third, and fourth dielectric layers.

5 . The method of claim 2 , wherein the first dielectric layer has a higher refractive index than the second, third, and fourth dielectric layers.

6 . The method of claim 5 , wherein refractive indices of the first dielectric layer and a sum of the refractive indices of the second, third, and fourth dielectric layers is greater than 1.45.

7 . The method of claim 2 , wherein the first, second, third, and fourth dielectric layers include silicon dioxide.

8 . The method of claim 7 , wherein an oxide to silicon ratio in the first dielectric layer is less than a sum of oxide to silicon ratios in the second, third, and fourth dielectric layers.

9 . The method of claim 8 , wherein the oxide to silicon ratio in the second, third, and fourth dielectric layers is between 1.7 to 2.3.

10 . The method of claim 9 , wherein the oxide to silicon ratio in the first dielectric layer is between 1.7 to 2.3.

11 . The method of claim 2 , wherein the first, second, third, and/or fourth dielectric layers are deposited by chemical vapor deposition (CVD).

12 . The method of claim 1 , wherein a ratio of a thickness of the first dielectric layer to a thickness of the first or second dies is between 0.01 to 0.4.

13 . The method of claim 1 , wherein a sum of a thickness of the first dielectric layer and a thickness of the first or second die is 15 μm or higher.

14 . The method of claim 1 , wherein the first die is an active die and the second die is a dummy die.

15 . A method of forming an integrated circuit structure, the method comprising:

bonding a first die to a first side of a semiconductor substrate;

bonding a second die to the first side of the semiconductor substrate, the second die being adjacent to the first die and a space being defined between the first die and second die;

forming a first dielectric layer over the first and second dies and in the space;

forming a first opening in the first dielectric layer in the space; and

forming a second dielectric layer over the first dielectric layer and in the first opening, wherein the first dielectric layer is thicker than the second dielectric layer in the space.

16 . The method of claim 15 , further comprising:

forming a second opening in the second dielectric layer over the first opening;

forming a third dielectric layer over the second dielectric layer and in the second opening;

forming a third opening in the third dielectric layer over the second opening;

forming a fourth dielectric layer over the third dielectric layer and in the third opening; and

forming a fourth opening in the fourth dielectric layer over the third opening, wherein the first dielectric layer is thicker than the second, third, and fourth dielectric layers in the space.

17 . The method of claim 16 , wherein an oxide to silicon ratio in the first dielectric layer is less than a sum of oxide to silicon ratios in the second, third, and fourth dielectric layers.

18 . The method of claim 15 , wherein the first die is an active die and the second die is a dummy die.

19 . An integrated circuit structure, comprising:

a first die bonded to a first side of a first substrate;

a dummy die bonded to the first side of the first substrate, a space being defined between the first die and the dummy die; and

a plurality of dielectric layers filling the space, wherein each layer of the plurality of layers includes silicon dioxide and a bottommost dielectric layer has a higher density than each of other dielectric layers in the space.

20 . The integrated circuit structure of claim 19 , wherein the bottommost dielectric layer has a higher film stress in absolute value than each of the other dielectric layers in the space.