IP Library Granted Patent US 12708031
Granted Patent B2
US 12708031 · App. 18/269,172 · Granted Aug 11, 2026

Semiconductor package and manufacturing method therefor

Inventors: Tae Sup Choi (Seoul, KR); Woon Kang (Seoul, KR); Jin Ho Yoon (Seoul, KR)
Assignee: LG INNOTEK CO., LTD.
H10W74/15H10W74/012H10W74/47H10W72/01223H10W72/01323H10W72/072H10W72/07231H10W72/07234H10W72/07236H10W72/07237H10W72/073H10W72/07334H10W72/07338H10W72/241H10W72/332H10W72/354H10W90/724H10W90/734H10W99/00
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Quick Facts
Patent No.
US 12708031
App. No.
18/269,172
Granted
Aug 11, 2026
Kind
B2
Abstract

A semiconductor package comprises: a printed circuit board including a connection portion; an IC chip arranged on the printed circuit board; a solder portion arranged on the lower surface of the IC chip and coupled to the connection portion; a bonding layer arranged between the solder portion and the connection portion; and an underfill arranged between the IC chip and the printed circuit board, wherein the bonding layer includes thermosetting resin, and the underfill include thermoplastic resin.

Claims (42)

1 . A semiconductor package comprising:

a printed circuit board including a connection portion;

an IC chip arranged on the printed circuit board;

a solder portion arranged on the lower surface of the IC chip and coupled to the connection portion;

a bonding layer arranged between the solder portion and the connection portion; and

an underfill arranged between the IC chip and the printed circuit board,

wherein the bonding layer includes thermosetting resin,

wherein the underfill includes thermoplastic resin,

wherein the bonding layer comprises printing epoxy on the printed circuit board in a form of a gel-type resin,

wherein the IC chip includes a first side, a second side opposing the first side, a third side connecting the first and second sides, and a fourth side opposing the third side,

wherein the underfill includes a first underfill that overlaps, in a vertical direction, the first side and at least a portion of the third and fourth sides, and a second underfill that overlaps, in the vertical direction, the second side and at least another portion of the third and fourth sides, and

wherein the first underfill and the second underfill are horizontally spaced apart from each other at the third side and the fourth side of the IC chip, respectively.

2 . The semiconductor package according to claim 1 ,

wherein the material of the bonding layer is epoxy.

3 . The semiconductor package according to claim 1 ,

wherein the material of the underfill is polyurethane.

4 . The semiconductor package according to claim 1 ,

wherein a thickness of the bonding layer in an up and down direction is smaller than half of the solder portion in an up and down direction.

5 . The semiconductor package according to claim 1 ,

wherein a thickness of the underfill in an up and down direction is greater than a thickness of the solder portion in an up and down direction.

6 . The semiconductor package according to claim 1 , wherein the underfill includes a cured thermoplastic resin applied along a circumference of the IC chip.

7 . The semiconductor package according to claim 1 , wherein the connection portion is a circuit pattern electrically connected to the IC chip.

8 . The semiconductor package according to claim 1 , wherein the solder portion has a ball shape.

9 . The semiconductor package according to claim 1 , wherein the bonding layer is hardened by a reflow process to bond the solder portion onto the connection portion.

10 . A manufacturing method of a semiconductor package comprising:

(a) supplying a printed circuit board;

(b) printing thermosetting resin on the printed circuit board;

(c) applying a solder paste to the printed circuit board;

(d) mounting an IC chip on the printed circuit board and applying thermoplastic resin around the IC chip; and

(e) curing the thermosetting resin and the thermoplastic resin,

wherein the thermoplastic resin comprises printing epoxy on the printed circuit board in a form of a gel-type resin,

wherein the IC chip includes a first side, a second side opposing the first side, a third side connecting the first and second sides, and a fourth side opposing the third side,

wherein the thermoplastic resin includes a first thermoplastic resin that overlaps, in a vertical direction, the first side and at least a portion of the third and fourth sides, and a second thermoplastic resin that overlaps, in the vertical direction, the second side and at least another portion of the third and fourth sides, and

wherein the first thermoplastic resin and the second thermoplastic resin are horizontally spaced apart from each other at the third side and the fourth side of the IC chip, respectively.

11 . The manufacturing method according to claim 10 ,

wherein the thermoplastic resin includes polyurethane, and

wherein the thermosetting resin includes epoxy.

12 . The manufacturing method according to claim 10 , further comprising:

inspecting mounting state of the IC chip after step (e).

13 . The manufacturing method according to claim 12 , further comprising:

dipping the IC chip in epoxy after step (c).

14 . The manufacturing method according to claim 10 , wherein in step (d), the thermoplastic resin is disposed to cover at least three sides of the IC chip.