IP Library Granted Patent US 12708039
Granted Patent B2
US 12708039 · App. 18/151,609 · Granted Aug 11, 2026

Method of manufacturing 3DIC package comprising a plurality of discrete device dies bonding to a wafer

Inventors: Ching-Yu Huang (Hsinchu, TW); Kuo-Chiang Ting (Hsinchu, TW); Ting-Chu Ko (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H10W90/00H10B80/00H10P54/00H10W40/22H10W74/014H10W74/114H10W74/121H10W70/65H10W72/0198H10W72/073H10W72/353H10W72/923H10W72/941H10W72/9415H10W72/944H10W72/951H10W72/952H10W72/953H10W80/312H10W80/327H10W80/743H10W90/297H10W90/734H10W90/736H10W90/792
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Quick Facts
Patent No.
US 12708039
App. No.
18/151,609
Granted
Aug 11, 2026
Kind
B2
Abstract

A method includes bonding a first device die to a second device die through face-to-face bonding, wherein the second device die is in a device wafer, forming a gap-filling region to encircle the first device die, performing a backside-grinding process on the device wafer to reveal a through-via in the second device die, and forming a redistribution structure on the backside of the device wafer. The redistribution structure is electrically connected to the first device die through the through-via in the second device die. A supporting substrate is bonded to the first device die.

Claims (41)

1 . A method comprising:

bonding a first device die to a second device die through face-to-face bonding, wherein the second device die is in a device wafer;

forming a gap-filling region to encircle the first device die;

performing a backside-grinding process on the device wafer to reveal a first through-via in the second device die;

forming a redistribution structure on a backside of the device wafer, wherein the redistribution structure is electrically connected to the first device die through the first through-via in the second device die;

bonding a supporting substrate to the first device die; and

performing a sawing process to saw the device wafer into a plurality of packages, wherein the first device die, the second device die, and a piece of the supporting substrate are comprised in a discrete package among the plurality of packages.

2 . The method of claim 1 , wherein the first device die comprises a semiconductor substrate, and the first device die is free from through-vias in the semiconductor substrate.

3 . The method of claim 1 , wherein the supporting substrate comprises a semiconductor substrate, and the supporting substrate is free from active devices and passive devices therein.

4 . The method of claim 1 , wherein the supporting substrate is comprised in a wafer, and the wafer is bonded to the first device die in a wafer-to-wafer bonding process.

5 . The method of claim 1 , wherein the discrete package further comprises a plurality of device dies overlapping the second device die, and the plurality of device dies are arranged as an array.

6 . The method of claim 1 , wherein the second device die further comprises a second through-via, wherein the first through-via is overlapped by the first device die, and the second through-via is overlapped by the gap-filling region.

7 . The method of claim 1 , wherein the bonding the first device die to the second device die is performed through both of dielectric-to-dielectric bonding and metal-to-metal bonding.

8 . The method of claim 1 , wherein the second device die comprises active devices.

9 . The method of claim 1 , wherein the second device die comprises passive devices, and the second device die is free from active devices.

10 . The method of claim 1 , wherein the supporting substrate comprises a metal plate.

11 . A method comprising:

forming a first device die comprising:

a first semiconductor substrate; and

first active devices on a first front surface of the first semiconductor substrate;

bonding a second device die to the first device die, wherein the second device die comprises:

a second semiconductor substrate;

second active devices on a second front surface of the second semiconductor substrate, wherein the first front surface and the second front surface face each other;

a first through-via penetrating through the second semiconductor substrate; and

an interconnect structure on a backside of the second device die; and

attaching a supporting substrate to the first device die, wherein at a time after the supporting substrate is attached, the first through-via comprises a wider end and a narrower end opposite to the wider end, and wherein the wider end is between the narrower end and the supporting substrate.

12 . The method of claim 11 , wherein the supporting substrate and the second device die are bonded to opposite sides of the first device die.

13 . The method of claim 11 , wherein the supporting substrate is free from active devices and passive devices therein.

14 . The method of claim 13 , wherein the supporting substrate comprises a silicon substrate.

15 . The method of claim 11 , further comprising:

dispensing a gap-filling dielectric material encircling the first device die, wherein the second device die comprises a second through-via penetrating through the second semiconductor substrate, and wherein the first device die overlaps the first through-via, and the gap-filling dielectric material overlaps the second through-via.

16 . A method comprising:

bonding a supporting substrate over a first device die, wherein the supporting substrate is free from active devices and passive devices therein;

attaching a metal feature over the supporting substrate through a thermal interface material, wherein the thermal interface material is in physical contact with the metal feature and a semiconductor substrate of the supporting substrate; and

bonding a second device die underlying the first device die, wherein the second device die comprises:

a through-via therein; and

a backside interconnect structure underlying and connected to the through-via.

17 . The method of claim 16 , wherein the metal feature comprises a metal cap or a heat sink.

18 . The method of claim 16 , wherein the through-via comprises a wider end and a narrower end opposite the wider end, and wherein the wider end is between the narrower end and the supporting substrate.

19 . The method of claim 16 , further comprising encapsulating the first device die in a dielectric gap-filling material, wherein the through-via is overlapped by the first device die, and wherein the second device die further comprises an additional through-via overlapped by the dielectric gap-filling material.

20 . The method of claim 16 , further comprising performing a sawing process to saw a device wafer that comprises the second device die into a plurality of packages, wherein the first device die, the second device die, and a piece of the supporting substrate are comprised in a discrete package of the plurality of packages.