Semiconductor package structure and method for fabricating the same
A semiconductor package structure includes a first package structure and a second package structure. The first package structure includes a chip stacking structure and a molding compound. A first conductive block is disposed on the chip stacking structure. The molding compound wraps the chip stacking structure and exposes the first conductive block. The second package structure is disposed on the chip stacking structure and electrically connected to the first conductive block. A gap is formed between the first package structure and the second package structure.
1 . A semiconductor package structure, comprising:
a first package structure, comprising a chip stacking structure and a molding compound, wherein a first conductive block is disposed on the chip stacking structure, and a molding compound wraps the chip stacking structure and exposes the first conductive block; and
a second package structure, disposed on the chip stacking structure and electrically connected to the first conductive block, wherein
a gap is formed between the first package structure and the second package structure;
wherein the first package structure further comprises:
a base plate, comprising an upper surface and a lower surface that are disposed opposite to each other, wherein the upper surface is provided with a first conductive pattern and the lower surface is provided with a second conductive pattern; and
the base plate further comprises a signal channel located between the upper surface and the lower surface, and the signal channel is connected to the first conductive pattern and the second conductive pattern;
wherein the chip stacking structure comprises:
a first chip, disposed on the base plate; and
a second chip, disposed on the first chip with an offset, the first chip and the second chip are respectively connected to the base plate by using lead wires, and the lead wires are located on a same side of the chip stacking structure.
2 . The semiconductor package structure of claim 1 , wherein the lead wires are connected to a same first conductive pattern.
3 . The semiconductor package structure of claim 1 , wherein the molding compound covers the lead wires.
4 . The semiconductor package structure of claim 1 , wherein a top surface of the first conductive block is lower than a top surface of the molding compound.
5 . The semiconductor package structure of claim 4 , wherein the second package structure is disposed on the first conductive block via a first solder ball, and the first solder ball protrudes from the molding compound.
6 . The semiconductor package structure of claim 1 , further comprising a filling layer, wherein the gap is filled with the filling layer.
7 . The semiconductor package structure of claim 6 , wherein a heat conductivity coefficient of the filling layer is greater than a heat conductivity coefficient of the molding compound.
8 . The semiconductor package structure of claim 6 , wherein a volume of a filler in the filling layer is less than a volume of a filler in the molding compound.
9 . The semiconductor package structure of claim 1 , wherein the first chip is disposed on the base plate via a bonding layer, and wherein the base plate further comprises a virtual channel, the bonding layer is located on the virtual channel, and a heat conductivity coefficient of the virtual channel is greater than a heat conductivity coefficient of the bonding layer.
10 . The semiconductor package structure of claim 9 , wherein the bonding layer comprises a first bonding layer and a second bonding layer, the second bonding layer is located on the first bonding layer, and an elastic modulus of the first bonding layer is less than an elastic modulus of the second bonding layer.
11 . A semiconductor package structure, comprising:
a first package structure, comprising a chip stacking structure and a molding compound, wherein a first conductive block is disposed on the chip stacking structure, and a molding compound wraps the chip stacking structure and exposes the first conductive block; and
a second package structure, disposed on the chip stacking structure and electrically connected to the first conductive block,
wherein a gap is formed between the first package structure and the second package structure;
wherein the semiconductor package structure comprises a filling layer, the gap is filled with the filler layer;
wherein a volume of a filler in the filling layer is less than a volume of a filler in the molding compound.
12 . The semiconductor package structure of claim 11 , wherein the chip stacking structure comprises:
a plurality of chips, each of which comprising a first surface and a second surface that are disposed opposite to each other, wherein the first conductive block is located on a first surface, a second conductive block is disposed on a second surface, and the first conductive block is connected to the second conductive block via a first signal hole.
13 . The semiconductor package structure of claim 12 , wherein a second conductive block at a bottom of the chip stacking structure is connected to the first conductive pattern via a second solder ball, and two adjacent chips are connected to each other via a second solder ball.
14 . The semiconductor package structure of claim 13 , wherein the molding compound is further located between two adjacent chips.
15 . The semiconductor package structure of claim 13 , wherein the base plate further comprises a virtual channel, and a second solder ball is connected to a second conductive pattern through the virtual channel.
16 . The semiconductor package structure of claim 12 , wherein the first conductive block is coplanar with the molding compound.
17 . The semiconductor package structure of claim 11 , wherein a heat conductivity coefficient of the filling layer is greater than a heat conductivity coefficient of the molding compound.