Memory stack structure including power distribution structures and a high-bandwidth memory including the memory stack structure

1 . A memory stack structure comprising:

a base die;

a bottom memory die stacked over the base die;

an intermediate memory die stacked over the bottom memory die;

a top memory die stacked over the intermediate memory die;

a signal transmission structure electrically connecting the base die, the bottom memory die, the intermediate memory die, and the top memory die to each other;

a first power distribution structure electrically connecting the base die to the bottom memory die; and

a second power distribution structure electrically connecting the bottom memory die, the intermediate memory die, and the top memory die to each other,

wherein the first power distribution structure is electrically connected to the second power distribution structure in the bottom memory die.

2 . The memory stack structure of claim 1 , wherein:

the bottom memory die includes a bottom memory circuit,

the intermediate memory die includes an intermediate memory circuit, and

the top memory die includes a top memory circuit,

wherein the bottom memory circuit, the intermediate memory circuit, and the top memory circuit are disposed areas vertically aligned and overlapped with the first power distribution structure, respectively.

3 . The memory stack structure of claim 2 ,

wherein the bottom memory circuit, the intermediate memory circuit, and the top memory circuit includes memory cells, respectively.

4 . The memory stack structure of claim 1 ,

wherein the base die further includes a base circuit disposed in an area vertically aligned and overlapped with the second power distribution structure.

5 . The memory stack structure of claim 1 , further comprising:

a third power distribution structure electrically connecting the base die, the bottom memory die, the intermediate memory die, and the top memory die to each other,

wherein the third power distribution structure includes:

a base third power bump over an upper surface of the base die;

a bottom lower third power bump under a lower surface of the bottom memory die;

a bottom third power via structure vertically passing though the bottom memory die;

a bottom upper third power bump over an upper surface of the bottom memory die;

an intermediate lower third power bump under a lower surface of the intermediate memory die;

an intermediate third power via structure vertically passing through the intermediate memory die;

an intermediate upper third power bump over an upper surface of the intermediate memory die; and

a top lower third power bump under a lower surface of the top memory die,

wherein the base third power bump, the bottom lower third power bump, the bottom third power via structure, the bottom upper third power bump, the intermediate lower third power bump, the intermediate third power via structure, the intermediate upper third power bump, and a top third power bump are vertically aligned and electrically connected to each other.

6 . The memory stack structure of claim 5 ,

wherein the first power distribution structure is electrically connected to the third power distribution structure in the bottom memory die.

7 . The memory stack structure of claim 5 ,

wherein the second power distribution structure is electrically connected to the third power distribution structure in the bottom memory die.

8 . The memory stack structure of claim 1 , wherein:

the base die includes a base first power distribution structure area vertically overlapping with the first power distribution structure,

the base first power distribution structure area is disposed, in a layout, adjacent to a corner of the base die,

the bottom memory die, the intermediate memory die, and the top memory die include memory first power distribution structure areas, respectively, and

the memory first power distribution structure areas are disposed, in a layout, adjacent to corners of the bottom memory die, the intermediate memory die, and the top memory die.

9 . The memory stack structure of claim 1 , wherein:

the base die includes a base circuit disposed, in a layout, adjacent to an edge of the base die,

the second power distribution structure is disposed, in a layout, in memory second power distribution structure areas adjacent to edges of the bottom memory die, the intermediate memory die, and the top memory die, respectively, and

the base circuit and the memory second power distribution structure areas are vertically aligned to each other.

10 . The memory stack structure of claim 1 ,

wherein the base die includes a base third power distribution structure area,

wherein each of the bottom memory die, the intermediate memory die, and the top memory die includes a memory third power distribution structure area disposed, in a layout, in a conduction area where vertical and horizontal core areas intersect between cell blocks arranged in a matrix shape,

wherein the base third power distribution structure area and the memory third power distribution structure areas are vertically aligned to each other.

11 . The memory stack structure of claim 1 , further comprising:

an intermediate bump disposed under a lower surface of the intermediate memory die to be vertically aligned with the first power distribution structure,

wherein the intermediate bump is electrically connected to the second power distribution structure in the intermediate memory die.

12 . The memory stack structure of claim 1 ,

wherein the second power distribution structure includes:

a bottom lower second power bump disposed under a lower surface of the bottom memory die;

a bottom second power via structure vertically penetrating the bottom memory die;

a bottom upper second power bump disposed over an upper surface of the bottom memory die;

an intermediate lower second power bump disposed under a lower surface of the intermediate memory die;

an intermediate second power via structure vertically penetrating the intermediate memory die;

an intermediate upper second power bump disposed over an upper surface of the intermediate memory die; and

a second power bump disposed under a lower surface of the top memory die, and

wherein the bottom lower second power bump, the bottom second power via structure, the bottom upper second power bump, the intermediate lower second power bump, the intermediate second power via structure, the intermediate upper second power bump, and a top lower second power bump are vertically aligned and electrically connected to each other.

13 . The memory stack structure of claim 12 ,

wherein the bottom upper second power bump and the intermediate lower second power bump are directly bonded to each other, and

wherein the intermediate upper second power bump and the top lower second power bump are directly bonded to each other.

14 . The memory stack structure of claim 13 , wherein:

the bottom memory die further includes a bottom upper bonding insulating layer surrounding a side surface of the bottom upper second power bump,

the intermediate memory die further includes an intermediate lower bonding insulating layer surrounding a side surface of the intermediate lower second power bump and an intermediate upper bonding insulating layer surrounding a side surface of the intermediate upper second power bump,

the top memory die further includes a top lower bonding insulating layer surrounding a side surface of the top lower second power bump,

the bottom upper bonding insulating layer and the intermediate lower bonding insulating layer are directly bonded to each other, and

the intermediate upper bonding insulating layer and the top lower bonding insulating layer are directly bonded to each other.

15 . The memory stack structure of claim 12 ,

wherein the bottom second power via structure includes:

a bottom metal via passing through a lower area of the bottom memory die to be electrically connected to the bottom lower second power bump;

a bottom through-silicon via (TSV) vertically passing through an upper area of the bottom memory die to be electrically connected to the bottom upper second power bump; and

a bottom TSV pad between the bottom metal via and the bottom TSV,

wherein a horizontal width of the bottom TSV pad is greater than a horizontal width of the bottom metal via and greater than a horizontal width of the bottom TSV,

wherein the intermediate second power via structure includes:

an intermediate metal via vertically passing through a lower area of the intermediate memory die to be electrically connected to the intermediate lower second power bump;

an intermediate TSV vertically passing through an upper area of the intermediate memory die to be electrically connected to the intermediate upper second power bump; and

an intermediate TSV pad between the intermediate metal via and the intermediate TSV,

wherein a horizontal width of the intermediate TSV pad is greater than a horizontal width of the intermediate metal via and greater than a horizontal width of the intermediate TSV.

16 . The memory stack structure of claim 12 , wherein:

the intermediate memory die includes an intermediate lower dummy bump disposed under the lower surface of the intermediate memory die to be vertically aligned with the first power distribution structure,

the intermediate lower dummy bump is electrically connected to the intermediate lower second power bump,

the top memory die includes a top lower dummy bump disposed under the lower surface of the top memory die to be vertically aligned with the first power distribution structure, and

the top lower dummy bump is electrically connected to the top lower second power bump.

17 . A memory stack structure comprising:

a base die;

a bottom memory die stacked over the base die;

an intermediate memory die stacked over the bottom memory die;

a top memory die stacked over the intermediate memory die;

a first power distribution structure electrically connecting the base die to the bottom memory die;

a second power distribution structure electrically connecting the bottom memory die, the intermediate memory die, and the top memory die to each other; and

a third power distribution structure electrically connecting the base die, the bottom memory die, the intermediate memory die, and the top memory die to each other,

wherein the first power distribution structure is electrically connected to the third power distribution structure in the bottom memory die.

18 . The memory stack structure of claim 17 , further comprising:

an intermediate bump disposed under a lower surface of the intermediate memory die to be vertically aligned with the first power distribution structure,

wherein the intermediate bump is electrically connected to the third power distribution structure in the intermediate memory die.

19 . A die stack structure comprising:

a first die;

a second die stacked over the first die;

a third die stacked over the second die;

a fourth die stacked over the third die;

a signal transmission structure electrically connecting the first die, the second die, the third die, and the fourth die to one another in series;

a first power distribution structure electrically connecting the second die, the third die, and the fourth die;

a second power distribution structure electrically connecting the first die, the second die, the third die, and the fourth die,

wherein the first power distribution structure is electrically connected to the second power distribution structure in each of the second die, third die, and fourth die.

20 . The die stack structure of claim 19 , further comprising:

a third power distribution structure electrically connecting the first die to the second die,

wherein the first power distribution structure is electrically connected to the third power distribution structure in the first die.