Fabricating method of semiconductor die with tapered sidewall in package
A method for forming a chip package structure. The method includes bonding first connectors over a front surface of a semiconductor wafer. The method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. The method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.
1 . A method for forming a chip package structure, comprising:
bonding a plurality of first connectors over a front surface of a semiconductor wafer;
dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form a plurality of semiconductor dies;
mounting first and second semiconductor dies in the plurality of semiconductor dies over a top surface of an interposer substrate, wherein a first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance; and
forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die.
2 . The method as claimed in claim 1 , wherein the semiconductor wafer is diced by an etching process.
3 . The method as claimed in claim 1 , wherein the semiconductor wafer is diced by a sawing process using a blade that has a thickness gradually reduced from a center of the blade to an edge of the blade.
4 . The method as claimed in claim 1 , wherein the semiconductor die is diced to form the first semiconductor die having a vertical contour at a lower portion of the first sidewall, and the second semiconductor die having a vertical contour at a lower portion of the second sidewall.
5 . The method as claimed in claim 1 , wherein forming the encapsulating layer comprises:
forming a molding compound material surrounding the first and second semiconductor dies; and
forming an underfill material extending between the first semiconductor die and the second semiconductor die and between the interposer substrate and the first and second semiconductor dies.
6 . The method as claimed in claim 1 , wherein forming the encapsulating layer comprises:
forming a molding compound material surrounding the first and second semiconductor dies and extending between the first semiconductor die and the second semiconductor die and between the interposer substrate and the first and second semiconductor dies.
7 . The method as claimed in claim 1 , wherein the semiconductor wafer is diced to form two homogeneous dies serving as the first semiconductor die and the second semiconductor die.
8 . The method as claimed in claim 1 , wherein the semiconductor wafer is diced to form two system-on-chip (SoC) dies or two memory dies serving as the first semiconductor die and the second semiconductor.
9 . The method as claimed in claim 1 , further comprising:
etching back the encapsulating layer to expose top surfaces of the first and the second semiconductor dies by a planarization process; and
forming a plurality of second connectors over a bottom surface of the interposer substrate.
10 . The method as claimed in claim 9 , wherein each of the plurality of second connectors is formed to have a size that is greater than a size of each of the plurality of first connectors.
11 . The chip package structure as claimed in claim 1 , wherein the interposer substrate comprises an insulating base layer and a passivation layer covering the insulating base layer, wherein a distance between two opposite out edges of the passivation layer is shorter than a distance between two opposite out edges of the interposer substrate.
12 . A method for forming a chip package structure, comprising:
dicing a semiconductor wafer to form a first semiconductor die and a second semiconductor die, wherein the first semiconductor die has a first tapered sidewall and a first vertical sidewall opposite to the first tapered sidewall, and the second semiconductor die has a second tapered sidewall and a second vertical sidewall opposite to the second tapered sidewall;
mounting the first and second semiconductor dies over an interposer substrate, wherein the first tapered sidewall faces the second tapered sidewall;
forming a first encapsulating layer over the interposer substrate between the first tapered sidewall and second tapered sidewall; and
forming a second encapsulating layer over the interposer substrate and extending along edges of the interposer substrate, to surround the first and the second semiconductor dies and the first encapsulating layer,
wherein top surfaces of the first and the second semiconductor dies are exposed from the first encapsulating layer and the second encapsulating layer, and
wherein the first encapsulating layer between the first tapered sidewall and second tapered sidewall has a top width and a bottom width less than the top width.
13 . The method as claimed in claim 12 , wherein a portion of the first encapsulating layer extends between the first semiconductor die and the interposer substrate and between the second semiconductor die and the interposer substrate.
14 . The method as claimed in claim 13 , wherein the portion of the first encapsulating layer has a first sidewall that is vertically aligned to the first vertical sidewall and a second sidewall that is vertically aligned to the second vertical sidewall.
15 . The method as claimed in claim 13 , wherein forming the first encapsulating layer comprises forming an underfill material over the interposer substrate and forming the second encapsulating layer comprises forming a molding compound material over the interposer substrate and extending along the edges of the interposer substrate, to surround the first and the second semiconductor dies and the first encapsulating layer.
16 . The method as claimed in claim 12 , wherein the interposer substrate comprises an insulating base layer and a passivation layer covering the insulating base layer, wherein an outer edge of the insulating base layer laterally extending beyond an outer edge of the passivation layer the passivation layer, and the method further comprises:
forming a plurality of electrical connectors in the passivation layer.
17 . A method for forming a chip package structure, comprising:
dicing a semiconductor wafer to form a first semiconductor die and a second semiconductor die, wherein the first semiconductor die has a first sidewall with a vertical contour and a second sidewall with a contour different than the vertical contour and opposite to the first sidewall, and the second semiconductor die has a third sidewall with a vertical contour and a fourth sidewall with a contour different than the vertical contour of the third sidewall and opposite to the third sidewall;
mounting the first semiconductor die and the second semiconductor die over an organic interposer substrate, wherein the second sidewall adjacent to and fourth sidewall;
forming a first encapsulating layer between and in direct contact with the second sidewall and the fourth sidewall and between the organic interposer substrate and the first and the second semiconductor dies, wherein a top area of a portion of the first encapsulating layer between the second sidewall and the fourth sidewall is greater than a bottom area of the portion of first encapsulating layer; and
forming a second encapsulating layer in contact with a top surface of the organic interposer substrate and surrounding the first and the second semiconductor dies, wherein the second encapsulating layer comprises a first portion in direct contact with the first sidewall and a second portion in direct contact with the third sidewall, and wherein each of the first portion and the second portion of the second encapsulating layer has a top width and a bottom width equal to the top width in a direction that is parallel to the top surface of the organic interposer substrate.
18 . The method as claimed in claim 17 , further comprising:
before mounting the first semiconductor die, dicing a semiconductor wafer to form the first semiconductor die having a tapered sidewall serving as the second sidewall and the second semiconductor die having a tapered sidewall serving as the fourth sidewall.
19 . The method as claimed in claim 17 , wherein after mounting the second semiconductor die and forming the encapsulating layer, the second sidewall and the fourth sidewall are symmetric with respect to a central line of the first encapsulating layer between the second sidewall and the fourth sidewall.
20 . The method as claimed in claim 17 , wherein after mounting the second semiconductor die and forming the encapsulating layer, a distance from the first sidewall to the third sidewall in the direction is equal to a width of the first encapsulating layer between the organic interposer substrate and the first and the second semiconductor dies in the direction.