Semiconductor package

1 . A semiconductor package comprising:

a substrate;

a first stack structure disposed on the substrate, and including a first chip, a second chip disposed on the first chip, and a third chip disposed on the second chip; and

a second stack structure disposed on the substrate, and including a fourth chip, a fifth chip disposed on the fourth chip, and a sixth chip disposed on the fifth chip,

wherein:

the first stack structure includes a controller,

at least one of the first chip, the second chip, and the third chip is a memory chip and at least one of the fourth chip, the fifth chip, and the sixth chip is a memory chip,

the number of memory chips in the second stack structure is greater than the number of memory chips in the first stack structure,

the sixth chip is horizontally offset relative to the fifth chip toward the first stack structure, and

an upper surface of the first stack structure and an upper surface of the second stack structure are coplanar or substantially coplanar.

2 . The semiconductor package of claim 1 , wherein:

the controller is an application-specific integrated circuit (ASIC), and

each of the first stack structure and the second stack structure includes a plurality of NAND flash memories.

3 . The semiconductor package of claim 1 , wherein the first chip is the controller, and each of the second chip and the third chip is a memory chip.

4 . The semiconductor package of claim 1 , wherein the controller includes one or more pads.

5 . The semiconductor package of claim 4 , further comprising a plurality of bonding wires configured to electrically connect the controller to memory chips included in the first stack structure.

6 . The semiconductor package of claim 5 , wherein memory chips in the second stack structure are electrically connected to the controller via the plurality of bonding wires.

7 . The semiconductor package of claim 1 , wherein:

the first stack structure is vertically stacked in a first diagonal direction,

a first subset of chips of the second stack structure is vertically stacked in a second diagonal direction that is opposite to the first diagonal direction, and

a second subset of chips of the second stack structure is vertically stacked in the first diagonal direction.

8 . The semiconductor package of claim 1 , wherein the controller is mounted on the substrate in a flip chip bonding manner.

9 . A semiconductor package comprising:

a substrate;

a first stack structure disposed on the substrate, and including a logic chip, a first chip disposed on the logic chip, and a second chip disposed on the first chip, wherein each of the first chip and the second chip is a memory chip; and

a second stack structure disposed on the substrate, and including a third chip, a fourth chip disposed on the third chip, and a fifth chip disposed on the fourth chip, wherein each of the third chip, the fourth chip, and the fifth chip is a memory chip,

wherein:

the number of memory chips in the second stack structure is greater than the number of memory chips in the first stack structure,

at least two memory chips are electrically connected to the substrate directly via bonding wires,

the second chip is horizontally offset relative to the first chip,

the fifth chip is horizontally offset relative to the fourth chip, and

an upper surface of the first stack structure and an upper surface of the second stack structure are substantially coplanar.

10 . The semiconductor package of claim 9 , wherein the logic chip is a controller.

11 . The semiconductor package of claim 9 , wherein at least two adjacent chips in at least one of the first stack structure and the second stack structure are vertically disposed with no horizontal offset.

12 . The semiconductor package of claim 9 , wherein the fifth chip is horizontally offset relative to the fourth chip toward the first stack structure.

13 . The semiconductor package of claim 9 , wherein the fourth chip is horizontally offset relative to the third chip, and

wherein an offset direction of the fourth chip relative to the third chip is opposite to an offset direction of the fifth chip relative to the fourth chip.

14 . The semiconductor package of claim 9 , wherein the logic chip is mounted on the substrate in a flip chip bonding manner.

15 . A semiconductor package comprising:

a substrate;

a first stack structure disposed on the substrate, and including a first chip, a second chip disposed on the first chip, and a third chip disposed on the second chip;

a second stack structure disposed on the substrate, and including a fourth chip, a fifth chip disposed on the fourth chip, and a sixth chip disposed on the fifth chip; and

a first wire electrically coupling the second chip and the substrate;

a second wire electrically coupling the fourth chip and the substrate; and

a third wire electrically coupling the sixth chip and the substrate,

wherein:

at least one of the first chip, the second chip, and the third chip is a memory chip and at least one of the fourth chip, the fifth chip, and the sixth chip is a memory chip,

the first stack structure includes a controller,

the number of memory chips in the second stack structure is greater than the number of memory chips in the first stack structure,

the second wire is positioned opposite to the third wire with respect to the second stack structure, and

the controller is mounted on the substrate in a flip chip bonding manner.

16 . The semiconductor package of claim 15 , wherein:

the fifth chip is horizontally offset relative to the fourth chip,

the sixth chip is horizontally offset relative to the fifth chip, and

an offset direction of the fifth chip relative to the fourth chip is opposite to an offset direction of the sixth chip relative to the fifth chip.

17 . The semiconductor package of claim 15 , wherein the third chip is horizontally offset relative to the second chip toward the second stack structure.

18 . The semiconductor package of claim 15 , wherein a thickness of the controller is different from a thickness of a memory chip included in the first stack structure.