IP Library › Granted Patent US 12708057

Granted Patent B2

US 12708057 · App. 18/340,556 · Granted Aug 11, 2026

Package comprising sidewall interconnects configured for power routing

Inventors: Xia Li (San Diego, CA); Xuefeng Zhang (San Diego, CA); Aniket Patil (San Diego, CA)

Assignee: QUALCOMM INCORPORATED

H10W90/701 H10W70/611 H10W70/657 H10W70/685 H10W74/117 H10W90/00 H10W90/724

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Quick Facts

Patent No.: US 12708057
App. No.: 18/340,556
Granted: Aug 11, 2026
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A device comprising a package. The package comprises a package substrate; a first integrated device coupled to the package substrate through a first plurality of bump interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of bump interconnects; and a plurality of side wall interconnects coupled to the encapsulation layer and the metallization portion.

Claims (68)

1 . A device comprising:

a package comprising:

a package substrate;

a first integrated device coupled to the package substrate through a first plurality of bump interconnects, wherein the first plurality of bump interconnects are coupled to and touch the first integrated device and the package substrate;

a plurality of post interconnects located at least partially in an encapsulation layer;

a metallization portion coupled to the plurality of post interconnects;

an encapsulation layer at least partially encapsulating the first integrated device, wherein the encapsulation layer is coupled to and touches the package substrate and the metallization portion;

a second integrated device coupled to the metallization portion through a second plurality of bump interconnects, wherein the second plurality of bump interconnects are coupled to and touch the second integrated device and the metallization portion; and

a plurality of side wall interconnects coupled to the encapsulation layer and the metallization portion.

2 . The device of claim 1 , further comprising:

a connector coupled to the package through a third plurality of bump interconnects, and

one or more wires coupled to the connector.

3 . The device of claim 2 ,

wherein a bump interconnect from the third plurality of bump interconnects is coupled to and touches a side wall interconnect from the plurality of side wall interconnects.

4 . The device of claim 2 , wherein a bump interconnect from the third plurality of bump interconnects is coupled to and touches a top portion of the package.

5 . The device of claim 2 , further comprising:

a board coupled to the package through a plurality of solder interconnects; and

a board connector coupled to the board, wherein the board connector is further coupled to the connector through the one or more wires.

6 . The device of claim 2 ,

wherein a first bump interconnect from the third plurality of bump interconnects is configured to provide a first electrical path for a first power,

wherein a second bump interconnect from the third plurality of bump interconnects is configured to provide a second electrical path for a second power, and

wherein a third bump interconnect from the third plurality of bump interconnects is configured to provide an electrical path for ground.

7 . The device of claim 6 ,

wherein the first bump interconnect is configured to be electrically coupled to the first integrated device, and

wherein the second bump interconnect is configured to be electrically coupled to the second integrated device.

8 . The device of claim 1

wherein the first integrated device comprises a first front side and a first back side, wherein the first front side of the first integrated device faces in a direction toward the package substrate,

wherein the second integrated device comprises a second front side and a second back side, wherein the second front side of the second integrated device is coupled to a first surface of the metallization portion through the second plurality of bump interconnects,

wherein the package further comprises a third integrated device comprising a third front side and a third back side,

wherein the third front side of the third integrated device is coupled to a second surface of the metallization portion through a third plurality of bump interconnects,

wherein the third back side of the third integrated device faces in a direction toward the first integrated device, and

wherein the third plurality of bump interconnects touch the third integrated device and the metallization portion.

9 . The device of claim 1 , wherein the plurality of side wall interconnects are coupled to the package substrate.

10 . The device of claim 1 , further comprising a second encapsulation layer that is coupled to and touches (i) the plurality of side wall interconnects and (ii) the second integrated device, wherein the second encapsulation layer at least partially encapsulates the second integrated device.

11 . A device comprising:

a package comprising:

a package substrate;

a first integrated device coupled to the package substrate through a first plurality of bump interconnects, wherein the first plurality of bump interconnects are coupled to and touches the first integrated device and the package substrate;

a plurality of post interconnects located at least partially in an encapsulation layer;

a metallization portion coupled to the plurality of post interconnects;

an encapsulation layer at least partially encapsulating the first integrated device, wherein the encapsulation layer is coupled to and touches the package substrate and the metallization portion,

a second integrated device coupled to the metallization portion through a second plurality of bump interconnects, wherein the second plurality of bump interconnects are coupled to and touches the second integrated device and the metallization portion; and

a plurality of package interconnects coupled to the encapsulation layer and the metallization portion, wherein the plurality of package interconnects are embedded in the encapsulation layer.

12 . The device of claim 11 , further comprising:

a connector coupled to the package through a third plurality of bump interconnects, and

one or more wires coupled to the connector.

13 . The device of claim 12 ,

wherein a bump interconnect from the third plurality of bump interconnects is coupled to and touches a package interconnect from the plurality of package interconnects.

14 . The device of claim 12 , wherein a bump interconnect from the third plurality of bump interconnects is coupled to and touches a top portion of the package.

15 . The device of claim 12 , further comprising: