Device with cell analysis
A computing device is provided. The computing device includes an electrode layer comprising a plurality of microelectrode arrays (MEAs), each MEA being configured with electrodes for stimulation and sensing of biological cells; an interposer layer comprising an interposer for a wiring connection between the plurality of MEAs and a substrate of the computing device; a circuit layer comprising a plurality of circuit chips configured to stimulate the cells and store excitement of the cells in response to the stimulation by corresponding electrodes; and a controller configured to control whether or how to connect the plurality of circuit chips to the plurality of MEAs.
1 . A computing device comprising:
an electrode layer comprising a plurality of microelectrode arrays (MEAs), each MEA being configured with electrodes for stimulation and sensing of biological cells;
an interposer layer comprising an interposer for a wiring connection between the plurality of MEAs and a substrate of the computing device;
a circuit layer comprising a plurality of circuit chips configured to stimulate the cells and store excitement of the cells in response to the stimulation by corresponding electrodes; and
a controller configured to control whether or how to connect the plurality of circuit chips to the plurality of MEAs.
2 . The computing device of claim 1 , wherein the interposer layer comprises the electrode layer with the interposer layer and the circuit layer being connected to each other by flip-chip bonding.
3 . The computing device of claim 1 ,
wherein the electrode layer is formed on one side of the substrate on which the interposer layer is formed, and
wherein the circuit layer is formed on the one side of the substrate or on an opposing side of the substrate.
4 . The computing device of claim 1 , wherein the controller is configured to determine whether or how to connect the plurality of circuit chips to the plurality of respective MEAs, based on at least one of a number of the electrodes used for the stimulation and the sensing of the cells, or based on positions of the electrodes used for the stimulation.
5 . The computing device of claim 1 , wherein the controller is configured to select a number of circuit chips used among the plurality of circuit chips and determine positions of the selected circuit chips, based on at least one of a number of the electrodes used for the stimulation and the sensing of the cells, or positions of the electrodes used for the stimulation.
6 . The computing device of claim 1 , wherein, based on whether the plurality of circuit chips are activated, the controller is configured to selectively use electrodes corresponding to an activated circuit chip among the plurality of MEAs.
7 . The computing device of claim 6 , wherein the electrodes corresponding to the activated circuit chip comprise at least one of:
electrodes positioned adjacent to each other in one MEA corresponding to the activated circuit chip;
electrodes spaced apart from each other in one MEA corresponding to the activated circuit chip; and
electrodes spaced apart from each other in a plurality of MEAs corresponding to the activated circuit chip.
8 . The computing device of claim 1 , wherein a number of the electrodes used for stimulation and an arrangement of the electrodes for the stimulation are determined based on bonding positions of corresponding circuit chips and a number of the corresponding circuit chips.
9 . The computing device of claim 1 , wherein the plurality of MEAs is packaged on the substrate by centrally integrated electrode pads.
10 . The computing device of claim 1 , wherein sizes of at least some of the plurality of MEAs are same or different from each other.
11 . The computing device of claim 1 , wherein respective types and sizes of at least some of the plurality of circuit chips are same or different from each other.
12 . The computing device of claim 1 , wherein the electrode layer and the interposer layer are connected by flip-chip bonding by at least one of a micro bump or a through silicon via (TSV) including a fine line width.
13 . The computing device of claim 1 , wherein the plurality of circuit chips and the interposer layer are connected to each other by at least one of a micro bump, a redistributed layer (RDL), or a through silicon via (TSV) including a fine line width.
14 . The computing device of claim 1 , wherein
an electrode pad for the plurality of MEAs is disposed on the interposer layer or an upper portion of the substrate, and
a bonding pad for the plurality of circuit chips is disposed on the upper portion of the substrate or a lower portion of the substrate.
15 . The computing device of claim 1 , wherein a total number of MEAs is same as a total number of circuit chips.
16 . The computing device of claim 1 , wherein the plurality of circuit chips and the plurality of MEAs are matched one-to-one or one-to-many.
17 . The computing device of claim 1 , wherein
the interposer layer comprises a redistributed layer (RDL), and
the plurality of circuit chips and the electrodes of the plurality of MEAs are connected to each other through the RDL.
18 . The computing device of claim 1 , wherein the substrate comprises one of a printed circuit board (PCB) and a silicon substrate.
19 . The computing device of claim 1 , wherein the plurality of MEAs are packaged to be waterproof.
20 . The computing device of claim 1 , further comprising:
a cell culture vessel comprising a cell culture medium that cultures the cells,
wherein the electrode layer and the cell culture vessel are disposed adjacent to each other.