Self heating extraction design and methodology with power consumption correction
A semiconductor device structure and methodology for determining a power consumption of the device structure and to extract accurate real temperatures due to self-heating effects. The semiconductor device structure includes a first transistor device formed as a heater device and an adjacent device such as a second transistor device or a semiconductor junction device. In the method, the first transistor device is operable at different operating states (e.g., off state or at different applied power levels), and at each state, an electrical characteristic is measured at the adjacent second transistor device or junction device. The electrical characteristic measured at the adjacent second semiconductor device is correlated to a power consumption of the first device while excluding a power consumption due to voltage drops due to resistance of connected metal layers, vias or contacts. Accurate thermal conductivity is thus achievable for better Design Technology Co-Optimization (DTCO) and device/circuit reliability evaluation.
1 . A semiconductor device comprising:
a first semiconductor transistor heater device having a drain region, a source region, the drain region and source region defining a device channel therebetween, and a gate region, the drain, source and gate regions configured to receive an electrical stimulus to place said first semiconductor transistor heater device in an on or off state;
a second semiconductor transistor device situated adjacent and electrically connected to the first semiconductor transistor heater device, wherein the first semiconductor transistor heater device is a first FET device and said second semiconductor transistor device is a second FET device, said drain region of said first semiconductor transistor device comprising:
a first drain region having a first drain contact via structure formed thereon, and
a second drain region, said first drain region and second drain region of said first semiconductor transistor device being separated by a dummy gate therebetween, and said first drain region and second drain region being electrically connected by first embedded one or more semiconductor nanosheet channel layers that are each surrounded by a dielectric material layer and suspended through said dummy gate and electrically connect the first drain region to the second drain region; and
said source region of the first semiconductor transistor heater device comprising a source region common to both said first FET and second FET devices, said source region having a second contact via structure formed thereon, the second semiconductor transistor device further comprising:
a further drain region having a third contact via structure formed thereon, the further drain region separated from said common source region and second contact via structure, said further drain region and common source region of said adjacent second semiconductor transistor device being separated by a further gate region therebetween, and said further drain region and common source region being electrically connected by second embedded one or more semiconductor nanosheet channel layers that are each surrounded by a dielectric material layer and suspended through said further gate region and electrically connect the further drain region to the common source region;
a fourth contact via structure formed atop the second drain region; and
a sensor operatively connected to said first semiconductor transistor heater device for measuring an electrical characteristic at said second semiconductor transistor device, wherein said sensor is a four-terminal Kelvin sensor structure operatively connected to said first semiconductor transistor heater device, said Kelvin sensor structure having first and second Kelvin terminals operable to connect to said first contact via and second contact via structures to apply voltage between said first drain region and said common source region, and having third and fourth kelvin terminals operable to connect to said third contact via and fourth contact via structures to measure the electrical characteristic between said second drain contact structure formed atop the second drain region and the further drain contact structure formed atop the further drain region, wherein the Kelvin sensor structure obtains an electrical characteristic measurement of the defined device channel of said first semiconductor transistor heater device while said first semiconductor transistor heater device is in an off or on state and that excludes a metal/contact resistance drop.
2 . The semiconductor device as claimed in claim 1 , wherein the drain region of said first semiconductor transistor heater device comprises a drain contact structure formed atop the drain region and the source region of said first semiconductor transistor heater device comprises a source contact structure formed atop the source region, and wherein
the drain contact of said first semiconductor transistor heater device comprising a first contact via structure; and
the source contact of the first semiconductor transistor heater device comprising a second contact via structure, said first and second contact via structures for connecting to a respective first and second Kelvin terminal configured to apply an electrical stimulus to said first semiconductor transistor heater device; and
said drain contact of said first semiconductor transistor heater device further comprising a third contact via structure spaced apart from said first contact via structure, and
said source contact of said first semiconductor transistor heater device further comprising a fourth contact via structure spaced apart from said second contact via structure, said third and fourth contact vias for connecting to a respective third and fourth Kelvin terminal configured for measuring an electrical parameter of said Kelvin sensor.
3 . The semiconductor device as claimed in claim 2 , wherein said electrical stimulus is a first voltage differential applied across a channel connecting the drain region and said source region of said first semiconductor transistor heater device, and said measured electrical characteristic comprises a second voltage differential, said second voltage differential used to determine a power consumption of the first semiconductor transistor heater device while said first transistor device is in an on or off state, wherein said power consumption determination excludes a power consumption due to voltage drops at said contact via structures and avoids a power consumption at any metal conductor connecting to contact via structures.
4 . The semiconductor device as claimed in claim 3 , wherein the first semiconductor transistor heater device is a nanosheet FinFET transistor comprising one or more nanosheet channel structures connected between said drain region and said source region and extending though said gate structure.
5 . The semiconductor device as claimed in claim 1 , wherein the drain region of said first semiconductor transistor heater device comprises:
a first drain region having a first drain contact structure formed on top the first drain region; and
a second drain region having a second drain contact structure formed on top the second drain region; and
a first dummy gate structure separating said first drain and second drain regions and drain contact structures; and
the source region of said first semiconductor transistor device comprises:
a first source region having a first source contact structure formed on top the first source region; and
a second source region having a second source contact structure formed on top the second source region; and
a second dummy gate structure separating said first source and second source regions and source contact structures.
6 . The semiconductor device as claimed in claim 5 , wherein
the first drain contact structure of said first semiconductor transistor heater device comprises a first drain contact via structure; and
the first source contact structure of said first semiconductor transistor heater device comprises a second contact via structure, said first and second contact via structures for connecting to a Kelvin sensor configured to apply an electrical stimulus; and
the second drain contact structure of said first semiconductor transistor heater device comprises a third contact via structure, and
the second source contact structure of said first semiconductor transistor heater device comprises a fourth contact via structure, said third and fourth contact via structures for connecting to a measuring device also function as Kelvin sensor for measuring an electrical characteristic of said first semiconductor transistor heater device or second semiconductor transistor device.
7 . The semiconductor device as claimed in claim 6 , wherein
said measured electrical characteristic comprising one or more of a voltage, current or resistance measurement for determining a power consumption component of the first semiconductor transistor heater device while said first semiconductor transistor heater device is in an off or on state, wherein said power consumption avoids a power consumption component due to a voltage drop at a said contact via structure and avoids a power consumption component due to any metal conductor connecting to a contact via structure.
8 . The semiconductor device as claimed in claim 6 , wherein the applied electrical stimulus is a first voltage differential and said measured electrical characteristic comprises:
a second voltage difference across a channel structure connecting the first drain region and the first source region.
9 . The semiconductor device as claimed in claim 8 , wherein the first semiconductor transistor heater device is a nanosheet FinFET transistor, said channel structure comprising one or more nanosheet channel structures directly connecting said first drain region and second drain and extending though said gate structure; and said first semiconductor transistor heater device further comprises:
one or more nanosheet channel structures connected between said first drain region and second drain region and extending said kelvin sensor wherein a voltage at said first drain region and second drain region are equal; and
one or more nanosheet channel structures connected between said first source region and second source region and extending said kelvin sensor wherein a voltage at said first source region and second source region are equal.
10 . The semiconductor device as claimed in claim 1 , wherein said gate structure of said first semiconductor transistor heater device comprises:
a gate contact via structure formed on top said gate structure, wherein a stimulus applied to one or more said first and second contact via structures and said gate contact via structure operably place said first semiconductor transistor heater device in said on or off state, said measured electrical characteristic used to determine a power consumption component of the first semiconductor transistor heater device while said first semiconductor transistor heater device is in the on or off state.
11 . The semiconductor device as claimed in claim 10 , wherein said electrical stimulus is a first voltage differential, said Kelvin sensor configured to measure an electrical characteristic comprising a second voltage difference between said third and fourth contact via structures while said first semiconductor transistor heater device in an off or on state, said second voltage difference used to determine a power consumption of said first semiconductor transistor heater device.
12 . The semiconductor device as claimed in claim 11 , wherein the measured electrical characteristic at said first semiconductor transistor heater device excludes a voltage drop due to a contact resistance at each said contact via structures and avoids a voltage drop component due to any metal conductor connecting to a contact via structure.
13 . The semiconductor device as claimed in claim 10 , wherein
the further drain region of said second semiconductor transistor device is doped with a first type doping material, and a further semiconductor region abutting said further drain region is doped with a second opposite type doping material to form a semiconductor junction device comprising oppositely doped regions.
14 . A computer-implemented method for determining a semiconductor transistor device characteristic comprising:
operatively connecting a sensor device to a first semiconductor transistor heater device and a second semiconductor transistor device situated adjacent said first semiconductor transistor heater device, said first semiconductor transistor heater device having a drain region, a source region, the drain region and source region defining a device channel therebetween, the drain, source and gate regions configured to receive an electrical stimulus to place said first semiconductor transistor heater device in an on or off state; and the second semiconductor transistor device situated adjacent and electrically connected to the first semiconductor transistor heater device, wherein the first semiconductor transistor heater device is a first FET device and said second semiconductor transistor device is a second FET device, said drain region of said first semiconductor transistor device comprising:
a first drain region having a first drain contact via structure formed thereon, and
a second drain region, said first drain region and second drain region of said first semiconductor transistor device being separated by a dummy gate therebetween, and said first drain region and second drain region being electrically connected by first embedded one or more semiconductor nanosheet channel layers that are each surrounded by a dielectric material layer and suspended through said dummy gate and electrically connect the first drain region to the second drain region; and
said source region of the first semiconductor transistor heater device comprising a source region common to both said first and second FET devices, said source region having a second contact via structure formed atop the common source region, the second semiconductor transistor device further comprising:
a further drain region having a third contact via structure formed thereon, the further drain region separated from said common source region and corresponding second contact via structure, said further drain region and common source region of said adjacent second semiconductor transistor device being separated by a further gate region therebetween, and said further drain region and common source region being electrically connected by second embedded one or more semiconductor nanosheet channel layers that are each surrounded by a dielectric material layer and suspended through said further gate region and electrically connect the further drain region to the common source region;
said second drain region having a fourth contact via structure formed atop the second drain region; and
wherein said sensor device is a four-terminal Kelvin sensor structure operatively connected to said first semiconductor transistor heater device, said Kelvin sensor structure having first and second Kelvin terminals operable to connect to said first contact via and second contact via structures and applying voltage between said first drain region and said common source region for placing said first semiconductor transistor heater device in an on or off state, and having third and fourth kelvin terminals operable to connect to said third contact via and fourth contact via structures to measure the electrical characteristic between said second drain contact structure formed atop the second drain region and the further drain contact structure formed atop the further drain region;
configuring the sensor device to apply an electrical stimulus to one or more said drain contact, source contact or gate region for placing said first semiconductor transistor heater device in an on or off state; and
measuring an electrical characteristic of said defined device channel of said first semiconductor transistor heater device while said first semiconductor transistor heater device is in said on or off state, said electrical characteristic used to correlate temperature to a corrected power consumption impact from first semiconductor transistor heater device, wherein the Kelvin sensor structure obtains an electrical characteristic measurement that excludes a metal/contact resistance drop.
15 . The computer-implemented method of claim 14 , wherein the configuring the sensor device to apply an electrical stimulus comprises:
altering the electrical stimulus applied to said drain, source and gate contact structures of said first semiconductor transistor heater device, said altering electrical stimulus achieving a different power level at said first semiconductor transistor heater device; and
measuring an electrical characteristic of said second semiconductor device while said first semiconductor transistor heater device is in said on or off state.
16 . The computer-implemented method of claim 15 , further comprising:
calibrating a real power consumed at said first semiconductor transistor heater device at each said different power level applied at said first semiconductor transistor heater device.
17 . The computer-implemented method of claim 16 , further comprising:
correlating a temperature of said first semiconductor transistor heater device at each said different power level applied at said first semiconductor transistor heater device.